Eduard Cerny

According to our database, Eduard Cerny authored at least 77 papers between 1974 and 2005.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2005

Supporting sequential assumptions in hybrid verification.

Eduard Cerny, Ashvin Dsouza, Kevin Harer, Pei-Hsin Ho, Hi-Keung Tony Ma

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

MDG-Based State Enumeration By Retiming And Circuit Transformation.

Otmane Aït Mohamed, Xiaoyu Song, Eduard Cerny, Sofiène Tahar, Zijian Zhou

J. Circuits Syst. Comput., 2004

Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs (MDGs).

Ying Xu, Xiaoyu Song, Eduard Cerny, Otmane Aït Mohamed

Comput. J., 2004

2003

On the non-termination of M-based abstract state enumeration.

Otmane Aït Mohamed, Xiaoyu Song, Eduard Cerny

Theor. Comput. Sci., 2003

2002

Variable ordering on multiway decision graphs.

Yi Feng, Eduard Cerny

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Term ordering problem on MDG.

Yi Feng, Eduard Cerny

Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

2000

Compositional verification of an ATM switch module using interface recognizer/suppliers (IRS).

M. S. Jahanpour, Eduard Cerny

Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

Model Reductions and a Case Study.

Jin Hou, Eduard Cerny

Proceedings of the Formal Methods in Computer-Aided Design, Third International Conference, 2000

1999

Modeling and formal verification of the Fairisle ATM switch fabricusing MDGs.

Sofiène Tahar, Xiaoyu Song, Eduard Cerny, Zijian Zhou, Michel Langevin, Otmane Aït Mohamed

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST.

Samir Boubezari, Eduard Cerny, Bozena Kaminska, Benoit Nadeau-Dostie

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Worst case tolerance analysis and CLP-based multifrequency test generation for analog circuits.

Abdessatar Abderrahman, Eduard Cerny, Bozena Kaminska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Improving Termination of MDG-Based Abstract State Enumeration via Term Schematization.

Sophie Renault, Eduard Cerny

Proceedings of the First International Workshop on Symbolic Model Checking, 1999

Synthesis of checker EFSMs from timing diagram specifications.

E. K. Ogoubi, Eduard Cerny

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Practical Application of Formal Verification Techniques on a Frame Mux/Demux Chip from Nortel Semiconductors.

Ying Xu, Eduard Cerny, Allan Silburt, A. Coady, Ying Liu, Philip Pownall

Proceedings of the Correct Hardware Design and Verification Methods, 1999

1998

Semantics and verification of action diagrams with linear timing.

Karim Khordoc, Eduard Cerny

ACM Trans. Design Autom. Electr. Syst., 1998

MDG-based Verification by Retiming and Combinational Transformations.

Otmane Aït Mohamed, Eduard Cerny, Xiaoyu Song

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints.

Fen Jin, Henrik Hulgaard, Eduard Cerny

Proceedings of the Formal Methods in Computer-Aided Design, 1998

Verification of Real Time Controllers Against Timing Diagram Specifications Using Constraint Logic Programming.

Eduard Cerny, Fen Jin

Proceedings of the 24th EUROMICRO '98 Conference, 1998

Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis.

Maroun Kassab, Eduard Cerny, Sidi Aourid, Thomas H. Krodel

Proceedings of the 1998 Design, 1998

Synthesis of interface controllers from timing diagram specifications.

Abdelhalim El-Aboudi, El Mostapha Aboulhamid, Eduard Cerny

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs.

Ying Xu, Eduard Cerny, Xiaoyu Song, Francisco Corella, Otmane Aït Mohamed

Proceedings of the Computer Aided Verification, 10th International Conference, 1998

1997

Solving Linear, Min and Max Constraint Systems Using CLP Based on Relational Interval Arithmetic.

Pierre Girodias, Eduard Cerny, William J. Older

Theor. Comput. Sci., 1997

Model partitioning and the performance of distributed timewarp simulation of logic circuits.

Jocelyn Cloutier, Eduard Cerny, F. Guertin

Simul. Pract. Theory, 1997

Multiway Decision Graphs for Automated Hardware Verification.

Francisco Corella, Zijian Zhou, Xiaoyu Song, Michel Langevin, Eduard Cerny

Formal Methods Syst. Des., 1997

CLP-based Multifrequency Test Generation for Analog Circuits.

Abdessatar Abderrahman, Eduard Cerny, Bozena Kaminska

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Verification with Abstract State Machines Using MDGs.

Eduard Cerny, Francisco Corella, Michel Langevin, Xiaoyu Song, Sofiène Tahar, Zijian Zhou

Proceedings of the Formal Hardware Verification - Methods and Systems in Comparison, 1997

Interface timing verification with delay correlation using constraint logic programming.

Pierre Girodias, Eduard Cerny

Proceedings of the European Design and Test Conference, 1997

On the non-termination of MDGs-based abstract state enumeration.

Otmane Aït Mohamed, Xiaoyu Song, Eduard Cerny

Proceedings of the Advances in Hardware Design and Verification, 1997

1996

A recursive technique for computing lower-bound performance of schedules.

Michel Langevin, Eduard Cerny

ACM Trans. Design Autom. Electr. Syst., 1996

Efficient generation of diagonal constraints for 2-D mask compaction.

Guy Bois, Eduard Cerny

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Optimization-based multifrequency test generation for analog circuits.

Abdessatar Abderrahman, Bozena Kaminska, Eduard Cerny

J. Electron. Test., 1996

Behavioral Verification of an ATM Switch Fabric using Implicit Abstract State Enumeration.

Michel Langevin, Sofiène Tahar, Zijian Zhou, Xiaoyu Song, Eduard Cerny

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Formal Verification of an ATM Switch Fabric using Multiway Decision Graphs.

Sofiène Tahar, Zijian Zhou, Xiaoyu Song, Eduard Cerny, Michel Langevin

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

Formal Verification of the Island Tunnel Controller Using Multiway Decision Graphs.

Zijian Zhou, Xiaoyu Song, Sofiène Tahar, Eduard Cerny, Francisco Corella, Michel Langevin

Proceedings of the Formal Methods in Computer-Aided Design, First International Conference, 1996

Bounding Switching Activity in CMOS Circuits Using Constraint Resolution.

Jindrich Zejda, Eduard Cerny, S. Shenoy, Nicholas C. Rumin

Proceedings of the 1996 European Design and Test Conference, 1996

MDG Tools for the Verification of RTL Designs.

K. D. Anon, N. Boulerice, Eduard Cerny, Francisco Corella, Michel Langevin, Xiaoyu Song, Sofiène Tahar, Ying Xu, Zijian Zhou

Proceedings of the Computer Aided Verification, 8th International Conference, 1996

1995

Partitioning transition relations efficiently and automatically.

Zijian Zhou, Xiaoyu Song, Francisco Corella, Eduard Cerny, Michel Langevin

Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

State enumeration with abstract descriptions of state machines.

Francisco Corella, Michel Langevin, Eduard Cerny, Zijian Zhou, Xiaoyu Song

Proceedings of the Correct Hardware Design and Verification Methods, 1995

1994

Fault Tolerance in a Class of Sorting Networks.

Jianli Sun, Eduard Cerny, Jan Gecsei

IEEE Trans. Computers, 1994

Use of Fault Dropping for Multiple Fault Analysis.

Younès Karkouri, El Mostapha Aboulhamid, Eduard Cerny, Alain Verreault

IEEE Trans. Computers, 1994

Modeling Cell Processing Hardware with Action Diagrams.

Karim Khordoc, Eduard Cerny

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Gate-level timing verification using waveform narrowing.

Jindrich Zejda, Eduard Cerny

Proceedings of the Proceedings EURO-DAC'94, 1994

An Extended OBDD Representation for Extended FSMs.

Michel Langevin, Eduard Cerny

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Local microcode generation in system design.

Michel Langevin, Eduard Cerny, Jörg Wilberg, Heinrich Theodor Vierhaus

Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994

1993

On the generation of test patterns for multiple faults.

El Mostapha Aboulhamid, Younès Karkouri, Eduard Cerny

J. Electron. Test., 1993

Integrating Behavior and Timing in Executable Specifications.

Karim Khordoc, Mario Dufresne, Eduard Cerny, P. A. Babkine, Allan Silburt

Proceedings of the Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, 1993

1992

Accuracy of magnitude-class calculations in switch-level modeling.

Eduard Cerny, John P. Hayes, Nicholas C. Rumin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Algorithm for the graph-partitioning problem using a problem transformation method.

Mohamed Meknassi, El Mostapha Aboulhamid, Eduard Cerny

Comput. Aided Des., 1992

Verification of I/O Trace Set Inclusion for a Class of Non-Deterministic Finite State Machines.

Eduard Cerny

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1991

A recursive technique for computing delays in series-parallel MOS transistor circuits.

Jean Paul Caisso, Eduard Cerny, Nicholas C. Rumin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

A Compositional Transformation for Formal Verification.

Eduard Cerny

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

A Stimulus/Response System Based on Hierarchical Timing Diagrams.

Karim Khordoc, Mario Dufresne, Eduard Cerny

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Design by similarity using transaction modeling and statistical techniques.

Anas Kabbaj, Eduard Cerny, Michel R. Dagenais, François Bouthillier

Proceedings of the conference on European design automation, 1991

Comparing Generic State Machines.

Michel Langevin, Eduard Cerny

Proceedings of the Computer Aided Verification, 3rd International Workshop, 1991

1990

Fault-tolerance in balanced sorting networks.

Jianli Sun, Jan Gecsei, Eduard Cerny

J. Electron. Test., 1990

Tautology Checking Using Cross-Controllability and Cross-Observability Relations.

Eduard Cerny, C. Mauras

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1989

Magnitude classes in switch-level modeling.

Eduard Cerny, John P. Hayes, Nicholas C. Rumin

Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

1988

Functional Description of Connector-Switch-Attenuator Networks.

Eduard Cerny, Jan Gecsei

IEEE Trans. Computers, 1988

An Algebraic Model for Asynchronous Circuits Verification.

Christian Berthet, Eduard Cerny

IEEE Trans. Computers, 1988

Built-in self-test of a CMOS ALU.

Eduard Cerny, El Mostapha Aboulhamid, Guy Bois, Jocelyn Cloutier

IEEE Des. Test, 1988

A class of fault-tolerant cellular permutation networks.

Mohsine Eleuldj, El Mostapha Aboulhamid, Eduard Cerny

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

1987

A Test Design Methodology for Protocol Testing.

Behçet Sarikaya, Gregor von Bochmann, Eduard Cerny

IEEE Trans. Software Eng., 1987

Self-Adjusting Networks for VLSI Simulation.

Jan Gecsei, Eduard Cerny

IEEE Trans. Computers, 1987

CHESHIRE: An Object-Oriented Integration of VLSI CAD Tools.

Louis-Philippe Demers, P. Jacques, S. Fauvel, Eduard Cerny

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1985

Simulation of MOS Circuits by Decision Diagrams.

Eduard Cerny, Jan Gecsei

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985

An object-oriented swicth-level simulator.

C. Roy, Louis-Philippe Demers, Eduard Cerny, Jan Gecsei

Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1984

Built-In Testing of One-Dimensional Unilateral Iterative Arrays.

El Mostapha Aboulhamid, Eduard Cerny

IEEE Trans. Computers, 1984

Some issues in protocol implementation testing.

Eduard Cerny

Comput. Commun. Rev., 1984

Use of Formal Specifications for Protocol Design, Implementation and Testing.

Gregor von Bochmann, Eduard Cerny, George Walter Gerber, Rachida Dssouli, Michel Maksud, B. H. Phan, Behçet Sarikaya, Jean-Marc Serre

Proceedings of the Protocol Specification, 1984

1983

A Class of Test Generators for Built-In Testing.

El Mostapha Aboulhamid, Eduard Cerny

IEEE Trans. Computers, 1983

1982

Experience with Formal Specifications Using an Extended State Transition Model.

Gregor von Bochmann, Eduard Cerny, Michel Gagné, Claude Jard, Alain Léveillé, Clement Lacaille, Michel Maksud, K. S. Raghunathan, Behçet Sarikaya

IEEE Trans. Commun., 1982

Some Experience with the Use of Formal Specifications.

Gregor von Bochmann, Eduard Cerny, Michel Gagné, Claude Jard, Alain Léveillé, Clement Lacaille, Michel Maksud, K. S. Raghunathan, Behçet Sarikaya

Proceedings of the Protocol Specification, 1982

1979

Synthesis of Minimal Binary Decision Trees.

Eduard Cerny, Daniel Mange, Eduardo Sanchez

IEEE Trans. Computers, 1979

1978

Controllability and Fault Observability in Modular Combinational Circuits.

Eduard Cerny

IEEE Trans. Computers, 1978

1977

An Approach to Unified Methodology of Combinational Switching Circuits.

Eduard Cerny, Miguel A. Marin

IEEE Trans. Computers, 1977

1976

Comments on "Equational Logic".

Eduard Cerny

IEEE Trans. Computers, 1976

1974

A Computer Algorithm for the Synthesis of Memoryless Logic Circuits.

Eduard Cerny, Miguel A. Marin

IEEE Trans. Computers, 1974