Henrique Kessler

Orcid: 0000-0002-1840-3794

According to our database1, Henrique Kessler authored at least 6 papers between 2020 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2022
Transistor-Level Radiation Hardening by Design Techniques in Complex Gates.
J. Circuits Syst. Comput., December, 2022

Transistor Reordering for Electrical Improvement in CMOS Complex Gates.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

Standard Cell and Supergates Designs: An Electrical Comparison on 4-Input Logic Functions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Evaluating the Impact of BTI on Hiding Countermeasures for DPA and DEMA Attacks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Evaluation of Non-Series-Parallel Structures for BTI-Aware Automated Design Methodologies.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020


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