Rafael Soares

Orcid: 0000-0001-9493-7272

According to our database1, Rafael Soares authored at least 43 papers between 2006 and 2024.

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Bibliography

2024
VLSI Architectures of Approximate Arithmetic Units Applied to Parallel Sensors Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024

2023
Evaluating the Reliability of Different Voting Schemes for Fault Tolerant Approximate Systems.
J. Electron. Test., August, 2023

AxPPA: Approximate Parallel Prefix Adders.
IEEE Trans. Very Large Scale Integr. Syst., 2023

Exploring Security Threats by Hardware-Faults in Approximate Arithmetic Computing.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

An Energy-Efficient StEFCal VLSI Design with Approximate Squarer and Divider Units.
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023

Accuracy-, Delay- and Area-Driven Evaluation of Lower-Part Approximate Parallel Prefix Adder.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

New Energy-Efficient 3-2 and 4-2 Approximate Adder Compressors Topologies.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

An Optimized VLSI Exponential Unit Design Exploring Efficient Arithmetic Operation Strategies.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

An Ultra Low-Energy VLSI Approximate Discrete Haar Wavelet Transform for ECG Data Compression.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

Alfaba: A Tangible Solution to Support Brazilian Dyslexic Students in their Literacy Process.
Proceedings of the IEEE Global Engineering Education Conference, 2023

2022
AxRSU: Approximate Radix-4 Squarer Unit.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Fault Tolerance Evaluation of Different Majority Voter Designs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Discrete Haar Wavelet Transform Hardware Design for Energy-Efficient Image Watermarking.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

Pruning-based Neural Network Reduction for Faster Profiling Side-Channel Attacks.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

An Efficient Exponential Unit Designed in VLSI CMOS with Custom Operators.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

Fast Chaotic Image Encryption with Simultaneous Permutation and Diffusion for IoT Applications.
Proceedings of the IEEE Global Communications Conference, 2022

2021
Echo State network based soft sensor for Monitoring and Fault Detection of Industrial Processes.
Comput. Chem. Eng., 2021

Evaluating the Impact of BTI on Hiding Countermeasures for DPA and DEMA Attacks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Integration of Security Standards in DevOps Pipelines: An Industry Case Study.
Proceedings of the Product-Focused Software Process Improvement, 2020

Optimizing the Montgomery Modular Multiplier for a Power- and Area-Efficient Hardware Architecture.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Evaluating Cell Library Sizing Methodologies for Ultra-Low Power Near-Threshold Operation in Bulk CMOS.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

2019
Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Phase Detection and Analysis among Multiple Program Inputs.
Proceedings of the Symposium on High Performance Computing Systems, 2018

Developing a Corporate Chatbot for a Customer Engagement Program: A Roadmap.
Proceedings of the Intelligent Computing Theories and Application, 2018

A Novel Sizing Method Aiming Security Against Differential Power Analysis.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
An energy-based attack flow for temporal misalignment coutermeasures on cryptosystems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Range segmentation to improve latency in parallel stochastic computing.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Low voltage low power current reference circuit for passive RFID applications.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

2014
Towards a Framework to Perform DPA Attack on GALS Pipeline Architectures.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Engenharia de Requisitos: Um Survey realizado no Porto Digital, Recife/Brasil.
Proceedings of the XVII Iberoamerican Conference on Software Engineering, 2014

2013
Gerenciamento de Requisitos em Scrum baseado em Test Driven Development.
Proceedings of Requirements Engineering@Brazil 2013, Rio de Janeiro, Brazil, July 16, 2013, 2013

Evolução de requisitos na metodologia ágil.
Proceedings of Requirements Engineering@Brazil 2013, Rio de Janeiro, Brazil, July 16, 2013, 2013

Information security aspects of public software.
Proceedings of the Fifth International Conference on Management of Emergent Digital EcoSystems, 2013

2011
A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines.
IEEE Des. Test Comput., 2011

2010
Arquitetura GALS pipeline para criptografia robusta a ataques DPA e DEMA.
PhD thesis, 2010

A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

2009
Evaluation on FPGA of triple rail logic robustness against DPA and DEMA.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Evaluating the robustness of secure triple track logic through prototyping.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Triple Rail Logic Robustness against DPA.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

2007
A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

SCAFFI: An intrachip FPGA asynchronous interface based on hard macros.
Proceedings of the 25th International Conference on Computer Design, 2007

2006
Infrastructure for dynamic reconfigurable systems: choices and trade-offs.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006


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