Vinicius V. Camargo

According to our database1, Vinicius V. Camargo authored at least 8 papers between 2018 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Transistor Reordering for Electrical Improvement in CMOS Complex Gates.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

Standard Cell and Supergates Designs: An Electrical Comparison on 4-Input Logic Functions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Fast Chaotic Image Encryption with Simultaneous Permutation and Diffusion for IoT Applications.
Proceedings of the IEEE Global Communications Conference, 2022

2021
Evaluating the Impact of BTI on Hiding Countermeasures for DPA and DEMA Attacks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Evaluation of Non-Series-Parallel Structures for BTI-Aware Automated Design Methodologies.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
A Novel Sizing Method Aiming Security Against Differential Power Analysis.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018


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