Leomar S. da Rosa Jr.
Orcid: 0000-0002-7150-5685
According to our database1,
Leomar S. da Rosa Jr.
authored at least 53 papers
between 2003 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
Evaluating the Reliability of Different Voting Schemes for Fault Tolerant Approximate Systems.
J. Electron. Test., August, 2023
Alfaba: A Tangible Solution to Support Brazilian Dyslexic Students in their Literacy Process.
Proceedings of the IEEE Global Engineering Education Conference, 2023
2022
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Standard Cell and Supergates Designs: An Electrical Comparison on 4-Input Logic Functions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
SmartDR: Algorithms and Techniques for Fast Detailed Routing with Good Design Rule Handling.
ACM Trans. Design Autom. Electr. Syst., 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020
Methods for Susceptibility Analysis of Logic Gates in the Presence of Single Event Transients.
Proceedings of the IEEE International Test Conference, 2020
Evaluation of Non-Series-Parallel Structures for BTI-Aware Automated Design Methodologies.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults.
Proceedings of the VLSI-SoC: New Technology Enabler, 2019
Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A New Technique Using Tunnel Shape Information to Improve Path Search in Detailed Routing.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018
Probabilistic Method for Reliability Estimation of SP- Networks considering Single Event Transient Faults.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
A post-processing methodology to improve the automatic design of CMOS gates at layout-level.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016
Topological characteristics of logic networks generated by a graph-based methodology.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016
2015
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015
2014
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
2013
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
2012
Evaluating two implementations of the component responsible for decoding video and audio in the Brazilian digital TV middleware.
Multim. Tools Appl., 2012
NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012
2011
A comparative analysis of media processing component implementations for the Brazilian digital TV middleware.
Int. J. Inf. Technol. Commun. Convergence, 2011
Tests and Performance Analysis of Media Processing Implementations for the Middleware of Brazilian Digital TV System Using Different Scenarios.
Proceedings of the 5th FTRA International Conference on Multimedia and Ubiquitous Engineering, 2011
2010
Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits.
Microelectron. J., 2010
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
Proceedings of the 28th International Conference on Computer Design, 2010
2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
2008
Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
2007
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
2006
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
2003
Proceedings of the On The Move to Meaningful Internet Systems 2003: OTM 2003 Workshops, 2003