Marcelo Schiavon Porto
Orcid: 0000-0003-3827-3023Affiliations:
- Federal University of Pelotas, Brazil
According to our database1,
Marcelo Schiavon Porto
authored at least 160 papers
between 2007 and 2023.
Collaborative distances:
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on inf.ufrgs.br
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on orcid.org
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Bibliography
2023
J. Real Time Image Process., June, 2023
IEEE Trans. Very Large Scale Integr. Syst., April, 2023
Multim. Tools Appl., 2023
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023
High-Throughput and Multiplierless Hardware Design for the AV1 Fractional Motion Estimation.
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023
Efficient Architecture for VVC Angular Intra Prediction based on a Hardware-Friendly Heuristic.
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023
Efficient Hardware Design for the VVC Affine Motion Compensation Exploiting Multiple Constant Multiplication.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
High-Throughput and Multiplierless Hardware Design for the AV1 Local Warped MC Interpolation.
Proceedings of the IEEE International Conference on Image Processing, 2023
2022
Quality-power configurable flexible coding order hardware design for real-time 3D-HEVC intra-frame prediction.
J. Real Time Image Process., 2022
Hardware Design for the Separable Symmetric Normalized Wiener Filter of the AV1 Decoder.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022
Proceedings of the Picture Coding Symposium, 2022
Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
Standard Cell and Supergates Designs: An Electrical Comparison on 4-Input Logic Functions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Fast Affine Motion Estimation for VVC using Machine-Learning-Based Early Search Termination.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 2022 IEEE International Conference on Image Processing, 2022
2021
Energy-Throughput Configurable Design for Video Processing Binary Arithmetic Encoder.
IEEE Trans. Circuits Syst. Video Technol., 2021
IEEE Open J. Circuits Syst., 2021
J. Real Time Image Process., 2021
Fast and energy-efficient approximate motion estimation architecture for real-time 4 K UHD processing.
J. Real Time Image Process., 2021
J. Real Time Image Process., 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the 2021 IEEE International Conference on Image Processing, 2021
2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
6WR: A Hardware Friendly 3D-HEVC DMM-1 Algorithm and its Energy-Aware and High-Throughput Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Multim. Tools Appl., 2020
UHD 8K energy-quality scalable HEVC intra-prediction SAD unit hardware using optimized and configurable imprecise adders.
J. Real Time Image Process., 2020
IEEE Des. Test, 2020
IEEE Des. Test, 2020
Power/QoS-Adaptive HEVC FME Hardware using Machine Learning-Based Approximation Control.
Proceedings of the 2020 IEEE International Conference on Visual Communications and Image Processing, 2020
Proceedings of the 2020 IEEE International Conference on Visual Communications and Image Processing, 2020
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020
A Hardware Design for 3D-HEVC Depth Intra Skip with Synthesized View Distortion Change.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020
A Low-Complexity Algorithm and Its Low-Power and High-Throughput Architecture for 3D-HEVC DMM-1 Encoding Tool.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Low-Power and Memory-Aware Approximate Hardware Architecture for Fractional Motion Estimation Interpolation on HEVC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
An Overview of Dedicated Hardware Designs for State-of-the-Art AV1 and H.266/VVC Video Codecs.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
RDE-MOGA: Automatic Selection of Rate-Distortion-Energy Control Points for Video Encoders Using Muti-Objetive Genetic Algorithm.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
Proceedings of the 28th European Signal Processing Conference, 2020
2019
Energy-Aware Motion and Disparity Estimation System for 3D-HEVC With Run-Time Adaptive Memory Hierarchy.
IEEE Trans. Circuits Syst. Video Technol., 2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Efficient reference frame compression scheme for video coding systems: algorithm and VLSI design.
J. Real Time Image Process., 2019
High-throughput and power-efficient hardware design for a multiple video coding standard sample interpolator.
J. Real Time Image Process., 2019
Performance evaluation of HEVC RCL applications mapped onto NoC-based embedded platforms.
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019
Proceedings of the 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2019
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019
Encoding Efficiency and Computational Cost Assessment of State-Of-The-Art Point Cloud Codecs.
Proceedings of the 2019 IEEE International Conference on Image Processing, 2019
Proceedings of the 2019 IEEE International Conference on Image Processing, 2019
Energy-Efficiency Exploration of Memory Hierarchy using NVMs for HEVC Motion Estimation.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
A New Hardware Friendly 2D-DCT HEVC Compliant Algorithm and its High Throughput and Low Power Hardware Design.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 27th European Signal Processing Conference, 2019
Compression Efficiency and Computational Cost Comparison between AV1 and HEVC Encoders.
Proceedings of the 27th European Signal Processing Conference, 2019
2018
Reference frame context-adaptive variable-length coder: a real-time hardware-friendly approach for lossless external memory bandwidth reduction in current video-coding systems.
J. Real Time Image Process., 2018
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018
A Power-Efficient and High-Throughput Hardware Design for 3D-HEVC Disparity Estimation.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018
ASIC power-estimation accuracy evaluation: A case study using video-coding architectures.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018
High-Throughput Binary Arithmetic Encoder using Multiple-Bypass Bins Processing for HEVC CABAC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
High-Throughput and Low-Power Integrated Direct/Inverse HEVC Quantization Hardware Design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 2018 IEEE International Conference on Image Processing, 2018
HEVC Residual Syntax Elements Generation Architecture for High-Throughput CABAC Design.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Power-Efficient and Memory-Aware Approximate Hardware Design for HEVC FME Interpolator.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018
2017
J. Real Time Image Process., 2017
Rate and Complexity-Aware Coding Scheme for Fixed-Camera Videos Based on Region-of-Interest Detection.
Proceedings of the 23rd Brazillian Symposium on Multimedia and the Web, 2017
Objective and Subjective Video Quality Assessment in Mobile Devices for Low-Complexity H.264/AVC Codecs.
Proceedings of the 23rd Brazillian Symposium on Multimedia and the Web, 2017
Proceedings of the 23rd Brazillian Symposium on Multimedia and the Web, 2017
Proceedings of the VII Brazilian Symposium on Computing Systems Engineering, 2017
Novel multiple bypass bins scheme for low-power UHD video processing HEVC binary arithmetic encoder architecture.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017
Low-power HEVC binarizer architecture for the CABAC block targeting UHD video processing.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017
Proceedings of the 19th IEEE International Workshop on Multimedia Signal Processing, 2017
Multiple early-termination scheme for TZ search algorithm based on data mining and decision trees.
Proceedings of the 19th IEEE International Workshop on Multimedia Signal Processing, 2017
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017
High-throughput HEVC intrapicture prediction hardware design targeting UHD 8K videos.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
A multiplierless parallel HEVC quantization hardware for real-time UHD 8K video coding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 25th European Signal Processing Conference, 2017
Proceedings of the 25th European Signal Processing Conference, 2017
Complexity reduction of 3D-HEVC based on depth analysis for background and ROI classification.
Proceedings of the 25th European Signal Processing Conference, 2017
2016
Low-power hardware design for the HEVC Binary Arithmetic Encoder targeting 8K videos.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016
Rate-distortion-complexity analysis for prediction unit modes in 3D-HEVC depth coding.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016
An HEVC multi-size DCT hardware with constant throughput and supporting heterogeneous CUs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016
High-throughput and memory-aware hardware of a sub-pixel interpolator for multiple video coding standards.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016
Complexity reduction for 3D-HEVC depth map coding based on early Skip and early DIS scheme.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
2015
DMMFast: a complexity reduction scheme for three-dimensional high-efficiency video coding intraframe depth map coding.
J. Electronic Imaging, 2015
Real-Time Architecture for HEVC Motion Compensation Sample Interpolator for UHD Videos.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015
A Low-Area and High-Throughput Intra Prediction Architecture for a Multi-Standard HEVC and H.264/AVC Video Encoder.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015
Memory-Aware and High-Throughput Hardware Design for the HEVC Fractional Motion Estimation.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015
S-GMOF: A gradient-based complexity reduction algorithm for depth-maps intra prediction on 3D-HEVC.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015
A multi-standard interpolation filter for motion compensated prediction on high definition videos.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015
A real-time architecture for reference frame compression for high definition video coders.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Conference on Image Processing, 2015
2014
Proceedings of the 2014 IEEE Visual Communications and Image Processing Conference, 2014
Proceedings of the 2014 IEEE Visual Communications and Image Processing Conference, 2014
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014
A Memory Energy Consumption Analysis of Motion Estimation Algorithms using Data Reuse in Video Coding Systems.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014
Memory bandwidth reduction for H.264 and HEVC encoders using lossless reference frame coding.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A new differential and lossless Reference Frame Variable-Length Coder: An approach for high definition video coders.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014
Complexity reduction for 3D-HEVC depth maps intra-frame prediction using simplified edge detector algorithm.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014
Proceedings of the IEEE International Conference on Acoustics, 2014
Cost function optimization and its hardware design for the Sample Adaptive Offset of HEVC standard.
Proceedings of the 22nd European Signal Processing Conference, 2014
2013
Iterative random search: a new local minima resistant algorithm for motion estimation in high-definition videos.
Multim. Tools Appl., 2013
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
A real time high definition architecture for the Variable-Length Reference Frame Decoder.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013
A fast hardware-friendly motion estimation algorithm and its VLSI design for real time ultra high definition applications.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013
A lossless approach for external memory bandwidth reduction in video coding systems and its VLSI architecture.
Proceedings of the 2013 IEEE International Conference on Multimedia and Expo, 2013
A hardware friedly motion estimation algorithm for the emergent HEVC standard and its low power hardware design.
Proceedings of the IEEE International Conference on Image Processing, 2013
An energy-efficient hardware design for lossless reference frame compression in video coders.
Proceedings of the 20th IEEE International Conference on Electronics, 2013
ES&IS: Enhanced Spread and Iterative Search hardware-friendly motion estimation algorithm for the HEVC Standard.
Proceedings of the 20th IEEE International Conference on Electronics, 2013
High throughput hardware design for the HEVC Fractional Motion Estimation Interpolation Unit.
Proceedings of the 20th IEEE International Conference on Electronics, 2013
2012
DMPDS: A Fast Motion Estimation Algorithm Targeting High Resolution Videos and Its FPGA Implementation.
Int. J. Reconfigurable Comput., 2012
High throughput hardware design for the Adaptive Loop Filter of the emerging HEVC video coding.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012
Spread and Iterative Search: A High Quality Motion Estimation Algorithm for High Definition Videos and Its VLSI Design.
Proceedings of the 2012 IEEE International Conference on Multimedia and Expo, 2012
High performance hardware architectures for the inverse Rotational Transform of the emerging HEVC standard.
Proceedings of the 19th IEEE International Conference on Image Processing, 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
2011
Two fast multi-point search algorithms for high quality motion estimation in high resolution videos.
Int. J. Inf. Technol. Commun. Convergence, 2011
Two Novel Algorithms for High Quality Motion Estimation in High Definition Video Sequences.
Proceedings of the 24th SIBGRAPI Conference on Graphics, 2011
An efficient ME architecture for high definition videos using the new MPDS algorithm.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011
Proceedings of EUROCON 2011, 2011
2010
Proceedings of the International Conference on Image Processing, 2010
2009
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
2008
Architectural design for the new QSDS with dynamic iteration control motion estimation algorithm targeting HDTV.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008
A high throughput and low cost diamond search architecture for HDTV motion estimation.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008
2007
High Throughput Hardware Architecture for Motion Estimation with 4: 1 Pel Subsampling Targeting Digital Television Applications.
Proceedings of the Advances in Image and Video Technology, Second Pacific Rim Symposium, 2007
High Throughput Architecture for Forward Transforms Module of H.264/AVC Video Coding Standard.
Proceedings of the 14th IEEE International Conference on Electronics, 2007