Hiroyoshi Tanabe

According to our database, Hiroyoshi Tanabe authored at least 3 papers between 2000 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

Mask 3D Parameter Prediction in EUV Lithography by Convolutional Neural Network.

Atsushi Takahashi, Moe Sugiyama, Masayuki Shimoda, Hiroyoshi Tanabe

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2025

2024

Development of a Lithography Simulation Tool Set in Various Optical Conditions for Source Mask Optimization.

Masaki Kuramochi, Yukihide Kohira, Hiroyoshi Tanabe, Tetsuaki Matsunawa, Chikaaki Kodama

IEEE Access, 2024

2000

A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme.

Yasuhiro Takai, Mamoru Fujita, Kyoichi Nagata, Satoshi Isa, Shigeyuki Nakazawa, Atsunori Hirobe, Hiroaki Ohkubo, Masato Sakao, Shinichi Horiba, Tadashi Fukase, Yoshihiro Takaishi, Makoto Matsuo, Masahiro Komuro, Tetsuya Uchida, Takashi Sakoh, Kanta Saino, Shirou Uchiyama, Yuichi Takada, Junichi Sekine, Nobuko Nakanishi, Takeshi Oikawa, Masahiko Igeta, Hiroyoshi Tanabe, Hidenobu Miyamoto, Takeo Hashimoto, Hiromu Yamaguchi, Kuniaki Koyama, Yasuo Kobayashi, Takashi Okuda

IEEE J. Solid State Circuits, 2000