Chikaaki Kodama

Orcid: 0000-0002-1955-7357

According to our database1, Chikaaki Kodama authored at least 29 papers between 2002 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2018
Subresolution Assist Feature Generation With Supervised Data Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017
A Fast Process-Variation-Aware Mask Optimization Algorithm With a Novel Intensity Modeling.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Intensity Difference Map (IDM) Accuracy Analysis for OPC Efficiency Verification and Further Enhancement.
IPSJ Trans. Syst. LSI Des. Methodol., 2017

A Routing Method Using Directed Grid-Graph for Self-Aligned Quadruple Patterning.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Lithography hotspot detection by two-stage cascade classifier using histogram of oriented light propagation.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
A Fast Mask Manufacturability and Process Variation Aware OPC Algorithm with Exploiting a Novel Intensity Estimation Model.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

A Machine Learning Based Framework for Sub-Resolution Assist Feature Generation.
Proceedings of the 2016 on International Symposium on Physical Design, 2016

Grid-based Self-Aligned Quadruple Patterning aware two dimensional routing pattern.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A fast manufacturability aware Optical Proximity Correction (OPC) algorithm with adaptive wafer image estimation.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Manufacturability-aware mask assignment in multiple patterning lithography.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Effective two-dimensional pattern generation for self-aligned double patterning.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Fast mask assignment using positive semidefinite relaxation in LELECUT triple patterning lithography.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Positive Semidefinite Relaxation and Approximation Algorithm for Triple Patterning Lithography.
Proceedings of the Algorithms and Computation - 25th International Symposium, 2014

A fast process variation and pattern fidelity aware mask optimization algorithm.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013
Self-Aligned Double and Quadruple Patterning-aware grid routing with hotspots control.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2008
The O-Sequence: Representation of 3D-Dissection.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

2007
Linear Programming-Based Cell Placement With Symmetry Constraints for Analog IC Layout.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

A fast algorithm for rectilinear block packing based on selected sequence-pair.
Integr., 2007

2006
Improved method of cell placement with symmetry constraints for analog IC layout design.
Proceedings of the 2006 International Symposium on Physical Design, 2006

Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Thermal Driven Module Placement Using Sequence-pair.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Minimizing the Number of Empty Rooms on Floorplan by Dissection Line Merge.
IEICE Trans. Inf. Syst., 2005

A Graph Based Soft Module Handling in Floorplan.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

2004
A novel encoding method into sequence-pair.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
An Improved Method of Convex Rectilinear Block Packing Based on Sequence-Pair.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Selected sequence-pair: an efficient decodable packing representation in linear time using sequence-pair.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
An Efficient Decoding Method of Sequence-Pair with Reduced Redundancy.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

An efficient decoding method of sequence-pair.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002


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