Hiroyuki Kobatake

According to our database, Hiroyuki Kobatake authored at least 3 papers between 2006 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs.

Koichi Takeda, Toshio Saito, Shinobu Asayama, Yoshiharu Aimoto, Hiroyuki Kobatake, Shinya Ito, Toshifumi Takahashi, Masahiro Nomura, Kiyoshi Takeuchi, Yoshihiro Hayashi

IEEE J. Solid State Circuits, 2011

2006

A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications.

Koichi Takeda, Yasuhiko Hagihara, Yoshiharu Aimoto, Masahiro Nomura, Yoetsu Nakazawa, Toshio Ishii, Hiroyuki Kobatake

IEEE J. Solid State Circuits, 2006

Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit.

Koichi Takeda, Hidetoshi Ikeda, Yasuhiko Hagihara, Masahiro Nomura, Hiroyuki Kobatake

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006