Koichi Takeda

According to our database, Koichi Takeda authored at least 11 papers between 1996 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

A 280nW, 100kHz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feedforward period control scheme.

Takashi Tokairin, Koichi Nose, Koichi Takeda, Koichiro Noguchi, Tadashi Maeda, Kazuyoshi Kawai, Masayuki Mizuno

Proceedings of the Symposium on VLSI Circuits, 2012

2011

Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs.

Koichi Takeda, Toshio Saito, Shinobu Asayama, Yoshiharu Aimoto, Hiroyuki Kobatake, Shinya Ito, Toshifumi Takahashi, Masahiro Nomura, Kiyoshi Takeuchi, Yoshihiro Hayashi

IEEE J. Solid State Circuits, 2011

2006

A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications.

Koichi Takeda, Yasuhiko Hagihara, Yoshiharu Aimoto, Masahiro Nomura, Yoetsu Nakazawa, Toshio Ishii, Hiroyuki Kobatake

IEEE J. Solid State Circuits, 2006

Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes.

Masahiro Nomura, Yoshifumi Ikenaga, Koichi Takeda, Yoetsu Nakazawa, Yoshiharu Aimoto, Yasuhiko Hagihara

IEEE J. Solid State Circuits, 2006

An Automatic Bi-Directional Bus Repeater Control Scheme Using Dynamic Collaborative Driving Techniques.

Masahiro Nomura, Taku Ohsawa, Koichi Takeda, Yoetsu Nakazawa, Yoshinori Hirota, Yasuhiko Hagihara, Naoki Nishi

IEICE Trans. Electron., 2006

Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit.

Koichi Takeda, Hidetoshi Ikeda, Yasuhiko Hagihara, Masahiro Nomura, Hiroyuki Kobatake

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2001

An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield.

Kenji Noda, Koichi Takeda, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hideaki Kawamoto, Nobuyuki Ikezawa, Yoshiharu Aimoto, Noritsugu Nakamura, Takahiro Iwasaki, Hideo Toyoshima, Tadahiko Horiuchi

IEEE J. Solid State Circuits, 2001

2000

A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro.

Koichi Takeda, Yoshiharu Aimoto, Noritsugu Nakamura, Hideo Toyoshima, Takahiro Iwasaki, Kenji Noda, Koujirou Matsui, Shinya Itoh, Sadaaki Masuoka, Tadahiko Horiuchi, Atsushi Nakagawa, Kenju Shimogawa, Hiroyuki Takahashi

IEEE J. Solid State Circuits, 2000

An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield.

Kenji Noda, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hiroyuki Kawamoto, Nobuyuki Ikezawa, Koichi Takeda, Yoshiharu Aimoto, Naoto Nakamura, Hideo Toyoshima, Takahiro Iwasaki, Tadahiko Horiuchi

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1997

A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O.

Kazuyuki Nakamura, Koichi Takeda, Hideo Toyoshima, Kenji Noda, Hiroaki Ohkubo, Tetsuya Uchida, Toshiyuki Shimizu, Toshiro Itani, Ken Tokashiki, Koji Kishimoto

IEEE J. Solid State Circuits, 1997

1996

A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM.

Hideo Toyoshima, Shigeru Kuhara, Koichi Takeda, Kazuyuki Nakamura, Hiloshi Okamura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki

IEEE J. Solid State Circuits, 1996