Kiyoshi Takeuchi

According to our database, Kiyoshi Takeuchi authored at least 6 papers between 2007 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

An Architectural Study for Inference Coprocessor Core at the Edge in IoT Sensing.

Daisuke Watanabe, Yuji Yano, Shintaro Izumi, Hiroshi Kawaguchi, Kiyoshi Takeuchi, Toshiro Hiramoto, Shoichi Iwai, Masami Murakata, Masahiko Yoshimoto

Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2018

Verification of the Injection Enhancement Effect in IGBTs by Measuring the Electron and Hole Currents Separately.

Takuya Hoshii, Kazuyoshi Furukawa, Kuniyuki Kakushima, Masahiro Watanabe, Naoyuki Shigvo, Takuya Saraya, Toshihiko Takakura, Kazuo Itou, Munetoshi Fukui, Shinichi Suzuki, Kiyoshi Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, Hiromichi Ohashi, Hiroshi Lwai

Proceedings of the 48th European Solid-State Device Research Conference, 2018

2017

Parallel nonvolatile programming of power-up states of SRAM cells.

Toshiro Hiramoto, Tomoko Mizutani, Kiyoshi Takeuchi, Masaharu Kobayashi

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2012

Impact of Discrete-Charge-Induced Variability on Scaled MOS Devices.

Kiyoshi Takeuchi

IEICE Trans. Electron., 2012

2011

Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs.

Koichi Takeda, Toshio Saito, Shinobu Asayama, Yoshiharu Aimoto, Hiroyuki Kobatake, Shinya Ito, Toshifumi Takahashi, Masahiro Nomura, Kiyoshi Takeuchi, Yoshihiro Hayashi

IEEE J. Solid State Circuits, 2011

2007

Source/Drain Optimization of Double Gate FinFET Considering GIDL for Low Standby Power Devices.

Katsuhiko Tanaka, Kiyoshi Takeuchi, Masami Hane

IEICE Trans. Electron., 2007