Masahiro Nomura
Orcid: 0000-0002-4945-5984
According to our database1,
Masahiro Nomura
authored at least 51 papers
between 1990 and 2024.
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Bibliography
2024
CoRR, 2024
2023
Proceedings of the International Conference on Machine Learning, 2023
CMA-ES with Learning Rate Adaptation: Can CMA-ES with Default Population Size Solve Multimodal and Noisy Problems?
Proceedings of the Genetic and Evolutionary Computation Conference, 2023
Proceedings of the Genetic and Evolutionary Computation Conference, 2023
2022
CMA-ES with Margin for Single-and Multi-Objective Mixed-Integer Black-Box Optimization.
CoRR, 2022
Optimal Fixed-Budget Best Arm Identification using the Augmented Inverse Probability Weighting Estimator in Two-Armed Gaussian Bandits with Unknown Variances.
CoRR, 2022
Proceedings of the Thirty-First International Joint Conference on Artificial Intelligence, 2022
Proceedings of the GECCO '22: Genetic and Evolutionary Computation Conference, Companion Volume, Boston, Massachusetts, USA, July 9, 2022
CMA-ES with margin: lower-bounding marginal probability for mixed-integer black-box optimization.
Proceedings of the GECCO '22: Genetic and Evolutionary Computation Conference, Boston, Massachusetts, USA, July 9, 2022
Proceedings of the Applications of Evolutionary Computation - 25th European Conference, 2022
Proceedings of the IEEE Congress on Evolutionary Computation, 2022
2021
Natural Evolution Strategy for Unconstrained and Implicitly Constrained Problems with Ridge Structure.
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2021
Proceedings of the CIKM '21: The 30th ACM International Conference on Information and Knowledge Management, Virtual Event, Queensland, Australia, November 1, 2021
Distance-weighted Exponential Natural Evolution Strategy for Implicitly Constrained Black-Box Function Optimization.
Proceedings of the IEEE Congress on Evolutionary Computation, 2021
Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021
2020
Evaluating Initialization of Nelder-Mead Method for Hyperparameter Optimization in Deep Learning.
Proceedings of the 25th International Conference on Pattern Recognition, 2020
2019
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019
2014
Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits.
IEEE J. Solid State Circuits, 2014
2013
Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: V<sub>DDmin</sub>-Aware Dual Supply Voltage Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2013
Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits.
IEEE J. Solid State Circuits, 2013
Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines.
IEEE J. Solid State Circuits, 2012
13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V<sub>DDmin</sub> limited ultra low voltage logic circuits.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs.
IEEE J. Solid State Circuits, 2011
Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Reduction of minimum operating voltage (V<sub>DDmin</sub>) of CMOS logic circuits with post-fabrication automatically selective charge injection.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V<sub>DD</sub>) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated V<sub>DD</sub> between flip-flops and combinational logics.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
A closed-form expression for estimating minimum operating voltage (V<sub>DDmin</sub>) of CMOS logic gates.
Proceedings of the 48th Design Automation Conference, 2011
2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
2008
A Circuit for Determining the Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit Operations.
IEEE J. Solid State Circuits, 2008
2006
IEEE J. Solid State Circuits, 2006
Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes.
IEEE J. Solid State Circuits, 2006
An Automatic Bi-Directional Bus Repeater Control Scheme Using Dynamic Collaborative Driving Techniques.
IEICE Trans. Electron., 2006
Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
1999
IEEE J. Solid State Circuits, 1999
1994
IEEE J. Solid State Circuits, December, 1994
IEEE J. Solid State Circuits, March, 1994
1990
Modular Design of Multiple-Valued Arithmetic VLSI System Using Signed-Digit Number System.
Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990