Masahiro Nomura

According to our database1, Masahiro Nomura authored at least 27 papers between 1990 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Simple and Scalable Parallelized Bayesian Optimization.
CoRR, 2020

Multi-Source Unsupervised Hyperparameter Optimization.
CoRR, 2020

2019
On Fail-Stop Signature Schemes with <i>H</i>-EUC Security.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

A Simple Heuristic for Bayesian Optimization with A Low Budget.
CoRR, 2019

Heat Transfer in Nanostructured Si and Heat Flux Control Technique.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2014
Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits.
IEEE J. Solid State Circuits, 2014

2013
Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: V<sub>DDmin</sub>-Aware Dual Supply Voltage Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits.
IEEE J. Solid State Circuits, 2013

Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Variation-aware subthreshold logic circuit design.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines.
IEEE J. Solid State Circuits, 2012

13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V<sub>DDmin</sub> limited ultra low voltage logic circuits.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs.
IEEE J. Solid State Circuits, 2011

Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Reduction of minimum operating voltage (V<sub>DDmin</sub>) of CMOS logic circuits with post-fabrication automatically selective charge injection.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V<sub>DD</sub>) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated V<sub>DD</sub> between flip-flops and combinational logics.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

A closed-form expression for estimating minimum operating voltage (V<sub>DDmin</sub>) of CMOS logic gates.
Proceedings of the 48th Design Automation Conference, 2011

2010
Misleading energy and performance claims in sub/near threshold digital systems.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2008
A Circuit for Determining the Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit Operations.
IEEE J. Solid State Circuits, 2008

2006
An Automatic Bi-Directional Bus Repeater Control Scheme Using Dynamic Collaborative Driving Techniques.
IEICE Trans. Electron., 2006

Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

1990
Modular Design of Multiple-Valued Arithmetic VLSI System Using Signed-Digit Number System.
Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990


  Loading...