Hongzhuo Liu

According to our database, Hongzhuo Liu authored at least 6 papers between 2022 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope.

Angxiao Yan, Wei Deng, Haikun Jia, Shiyan Sun, Chao Tang, Bufan Zhu, Yu Fu, Hongzhuo Liu, Baoyong Chi

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

An 11.5-to-14.3GHz 192.8dBc/Hz FoM at 1MHz Offset Dual-Core Enhanced Class-F VCO with Common-Mode-Noise Self-Cancellation and Isolation Technique.

Qixiu Wu, Wei Deng, Haikun Jia, Hongzhuo Liu, Shiwei Zhang, Zhihua Wang, Baoyong Chi

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 4.8-GHz Time-Interleaved Multi-Reference PLL with 16.1-fs Jitter.

Hongzhuo Liu, Wei Deng, Haikun Jia, Shiwei Zhang, Shiyan Sun, Baoyong Chi

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS.

Shiwei Zhang, Wei Deng, Haikun Jia, Hongzhuo Liu, Shiyan Sun, Pingda Guan, Baoyong Chi

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

IEEE ASSCC 2023/ Session 10/ Paper 10.5.

Ruichang Ma, Haikun Jia, Hongzhuo Liu, Wei Deng, Zhihua Wang, Baoyong Chi

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2022

A 4.7GHz Synchronized-Multi-Reference PLL with In-Band Phase Noise Lower than Reference Phase Noise +20logN_div.

Hongzhuo Liu, Wei Deng, Haikun Jia, Shiyan Sun, Qixiu Wu, Jiajie Tang, Zhihua Wang, Baoyong Chi

Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022