Wei Deng
Orcid: 0000-0002-6323-4539Affiliations:
- Tsinghua University, Institute of Microelectronics, Beijing, China
- Tokyo Institute of Technology, Department of Electrical and Electronic Engineering, Japan (PhD 2013)
- Apple Inc., Cupertino, CA, USA
According to our database1,
Wei Deng
authored at least 101 papers
between 2011 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
A Low-Phase-Noise VCO With Common-Mode Resonance Expansion and Intrinsic Differential 2nd-Harmonic Output Based on a Single Three-Coil Transformer.
IEEE J. Solid State Circuits, January, 2024
19.5 A 13.7-to-41.5GHz 214.1dBc/Hz FoMT Quad-Core Quad-Mode VCO Using an Oscillation-Mode-Splitting Technique.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 24-30-GHz Four-Element Phased Array Transceiver With Low Insertion Loss Compact T/R Switch and Bidirectional Phase Shifter for 5G Communication.
IEEE Trans. Very Large Scale Integr. Syst., November, 2023
A Compact and Low Phase Noise Square-Geometry Quad-Core Class-F VCO Using Parallel Inductor-Sharing Technique.
IEEE J. Solid State Circuits, October, 2023
A Low-Phase-Noise Quad-Core Millimeter-Wave Fundamental VCO Using Circular Triple-Coupled Transformer in 65-nm CMOS.
IEEE J. Solid State Circuits, February, 2023
IEEE J. Solid State Circuits, February, 2023
An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1<sup>st</sup>/2<sup>nd</sup>-Order DTC INL Calibration.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
An 11.5-to-14.3GHz 192.8dBc/Hz FoM at 1MHz Offset Dual-Core Enhanced Class-F VCO with Common-Mode-Noise Self-Cancellation and Isolation Technique.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 6.5-to-8GHz IEEE 802.15.4z-compliant All-Digital UWB Transmitter with Integrated Fast-Settling Master-Slave Regulator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
INVITED PAPER: A 312.5Mbps-32Gbps JESD204C Wireline Transceiver Back-Compatible with JESD204B in 28nm CMOS.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A 37-to-41.8 GHz Double-Gm-Boosting LNA with 2.9-dB NFmin Using Quadruple-Coupling Transformer for Phased-Array Transceivers.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 25.0-to-35.9GHz Dual-Layer Quad-Core Dual-Mode VCO with 189.1dBc/Hz FoM and 200.2dBc/Hz FoMT at 1MHz Offset in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A Transient Enhancement Digital LDO with Adaptive Ripple Cancelation Based on Optimal Compensation Period Approximation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
A 27-to-31.6 GHz 8-Element Phased-Array Transmitter Front-End with Inter-Element-Interference Cancellation Scheme in 65 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
A Compact E-Band Load-Modulation Balanced Power Amplifier Using Coupled Transmission-Line Output Network Achieving 22.1-dBm Psat and 34.9%/12.2% Efficiency at Psat/6-dB PBO.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
A Fully Integrated Bit-to-Bit 24/48Gb/s QPSK/16-QAM D-Band Transceiver with Mixed-Signal Baseband in 28nm CMOS Technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
A 4.4-GHz 193.2-dB FoM 8-Shaped-Inductor Based LC-VCO Using Orthogonal-Coupled Triple-Coil Transformer.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Self-Adapted Two-Point Modulation Type-II Digital PLL for Fast Chirp Rate and Wide Chirp-Bandwidth FMCW Signal Generation.
IEEE J. Solid State Circuits, 2022
A 53.6-to-60.2GHz Many-Core Fundamental Oscillator With Scalable Mesh Topology Achieving -136.0dBc/Hz Phase Noise at 10MHz Offset and 190.3dBc/Hz Peak FoM in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A Highly Linearized Ka-band Heterodyne Receiver using a Folded Class-AB Inductive Peaking Mixer and Magnetic-Self-Cancellation-Transformer-Based IF Amplifiers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A 22.8 GHz to 32.8 GHz Compact Power Amplifier with a 15 dBm Output P1dB and 36.5% Peak PAE in 65-nm CMOS.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022
A 4.7GHz Synchronized-Multi-Reference PLL with In-Band Phase Noise Lower than Reference Phase Noise +20logN<sub>div</sub>.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
A 12.5-to-15.4GHz, -118.9dBc/Hz PN at 1MHz offset, and 191.0dBc/Hz FoM VCO with Common-Mode Resonance Expansion and Simultaneous Differential 2ND-Harmonic Output using a Single Three-Coil Transformer in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
A 76-81 GHz FMCW 2TX/3RX Radar Transceiver with Integrated Mixed-Mode PLL and Series-Fed Patch Antenna Array.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
A 0.85mm<sup>2</sup> BLE Transceiver Using an On-Chip Harmonic-Suppressed RFIO Circuitry With T/R Switch.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A 122-168GHz Radar/Communication Fusion-Mode Transceiver with 30GHz Chirp Bandwidth, 13dBm Psat, and 8.3dBm OP1dB in 28nm CMOS.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A 11.1-to-14.2 GHz Self-adapted Two-point Modulation Dual-path Type-II Digital PLL Concurrently Achieving 124.7-MHz/μs Chirp Rate and 2.27-GHz Bandwidth.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A 60GHz 186.5dBc/Hz FoM Quad-Core Fundamental VCO Using Circular Triple-Coupled Transformer with No Mode Ambiguity in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A C-band FMCW Radar Transmitter with a 22 dBm Output Power Series-stacking CMCD PA for Long-distance Detection in 180-nm CMOS Technology.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
Optimization methods for high inductance-density inductors for high speed integrated circuits.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
An Ultra-Compact 16-to-45 GHz Power Amplifier within A Single Inductor Footprint Using Folded Transformer Technique.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
An 8.2-to-21.5 GHz Dual-Core Quad-Mode Orthogonal-Coupled VCO with Concurrently Dual-Output using Parallel 8-Shaped Resonator.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
A 24-30GHz 4-Element Phased Array Transceiver with Low Insertion Loss Compact T/R Switch and Bidirectional Phase Shifter in 65 nm CMOS Technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
A 33.5-37.5 GHz 4-Element Phased-Array Transceiver Front-End with High-Accuracy Low-Variation 6-bit Resolution 360° Phase Shift and 0~31.5 dB Gain Control in 65 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
A Highly Integrated Energy-efficient CMOS Millimeter-wave Transceiver with Direct-modulation Digital Transmitter, Quadrature Phased-coupled Frequency Synthesizer and Substrate-Integrated Waveguide E-shaped Patch Antenna.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
A 35-GHz TX and RX Front End With High TX Output Power for Ka-Band FMCW Phased-Array Radar Transceivers in CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2020
A 77-GHz Mixed-Mode FMCW Generator Based on a Vernier TDC With Dual Rising-Edge Fractional-Phase Detector.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
A U-Band PLL Using Implicit Distributed Resonators for Sub-THz Wireless Transceivers in 40 nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A CMOS 76-81-GHz 2-TX 3-RX FMCW Radar Transceiver Based on Mixed-Mode PLL Chirp Generator.
IEEE J. Solid State Circuits, 2020
An Energy-Efficient 10-Gb/s CMOS Millimeter-Wave Transceiver With Direct-Modulation Digital Transmitter and I/Q Phase-Coupled Frequency Synthesizer.
IEEE J. Solid State Circuits, 2020
A FoM of -191 dB, 4.4-GHz LC-VCO Integrating an 8-Shaped Inductor with an Orthogonal-Coupled Tail-Filtering Inductor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A 53.1-to-64.5 GHz In-Phase Coupled Quadrature Injection-Locked Oscillator with Transformer-Based I/Q-Phase Differential Injection Scheme.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
A 44-52 GHz Reflection-type Phase Shifter with 1.4° Phase Resolution in 28nm CMOS Process.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
2019
A 265- $\mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS.
IEEE J. Solid State Circuits, 2019
A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
IEEE J. Solid State Circuits, 2018
A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS.
IEEE J. Solid State Circuits, 2018
A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS.
IEICE Trans. Electron., 2018
A 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of -246dB for IoT applications in 65nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
An ADPLL-centric bluetooth low-energy transceiver with 2.3mW interference-tolerant hybrid-loop receiver and 2.9mW single-point polar transmitter in 65nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 0.85mm<sup>2</sup> BLE Transceiver with Embedded T/R Switch, 2.6mW Fully-Passive Harmonic Suppressed Transmitter and 2.3mW Hybrid-Loop Receiver.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
2017
IEICE Trans. Electron., 2017
An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
IEEE J. Solid State Circuits, 2016
A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad.
IEEE J. Solid State Circuits, 2016
A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB.
IEEE J. Solid State Circuits, 2016
A 0.0055mm<sup>2</sup> 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI.
IEICE Trans. Electron., 2016
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique.
IEEE J. Solid State Circuits, 2015
A 60-GHz CMOS Transmitter with Gain-Enhanced On-Chip Antenna for Short-Range Wireless Interconnections.
IEICE Trans. Electron., 2015
A Constant-Current-Controlled Class-C Voltage-Controlled Oscillator using Self-Adjusting Replica Bias Circuit.
IEICE Trans. Electron., 2015
A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI.
IEICE Electron. Express, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
14.1 A 0.048mm<sup>2</sup> 3mW synthesizable fractional-N PLL with a soft injection-locking technique.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular.
Proceedings of the ESSCIRC Conference 2015, 2015
A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of -246dB.
Proceedings of the ESSCIRC Conference 2015, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration.
IEEE J. Solid State Circuits, 2014
A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios.
IEEE J. Solid State Circuits, 2014
15.1 A 0.0066mm<sup>2</sup> 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the ESSCIRC 2014, 2014
A 0.015-mm<sup>2</sup> 60-GHz reconfigurable wake-up receiver by reusing multi-stage LNAs.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
A 0.011 mm<sup>2</sup> PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
A Sub-Harmonic Injection-Locked Quadrature Frequency Synthesizer With Frequency Calibration Scheme for Millimeter-Wave TDD Transceivers.
IEEE J. Solid State Circuits, 2013
Class-C VCO With Amplitude Feedback Loop for Robust Start-Up and Enhanced Oscillation Swing.
IEEE J. Solid State Circuits, 2013
A 20 GHz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique for a 60 GHz Frequency Synthesizer.
IEICE Trans. Electron., 2013
A 0.022mm<sup>2</sup> 970µW dual-loop injection-locked PLL with -243dB FOM using synthesizable all-digital PVT calibration circuits.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 13.2% locking-range divide-by-6, 3.1mW, ILFD using even-harmonic-enhanced direct injection technique for millimeter-wave PLLs.
Proceedings of the ESSCIRC 2013, 2013
A sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for use in 60GHz TDD transceivers.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
A fractional-N harmonic injection-locked frequency synthesizer with 10MHz-6.6GHz quadrature outputs for software-defined radios.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
A 0.5-V, 0.05-to-3.2 GHz LC-Based Clock Generator for Substituting Ring Oscillators under Low-Voltage Condition.
IEICE Trans. Electron., 2012
A 58.1-to-65.0GHz frequency synthesizer with background calibration for millimeter-wave TDD transceivers.
Proceedings of the 38th European Solid-State Circuit conference, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
A feedback class-C VCO with robust startup condition over PVT variations and enhanced oscillation swing.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
An ultra-low-voltage LC-VCO with a frequency extension circuit for future 0.5-V clock generation.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011