Shiyan Sun
According to our database1,
Shiyan Sun
authored at least 24 papers
between 2007 and 2023.
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Bibliography
2023
IEEE J. Solid State Circuits, February, 2023
An Intelligent Classification Approach via Multiple Classifier Fusion and Its Application to the Fault Diagnosis.
IEEE Access, 2023
An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A Fully Integrated Bit-to-Bit 24/48Gb/s QPSK/16-QAM D-Band Transceiver with Mixed-Signal Baseband in 28nm CMOS Technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
A Self-Adapted Two-Point Modulation Type-II Digital PLL for Fast Chirp Rate and Wide Chirp-Bandwidth FMCW Signal Generation.
IEEE J. Solid State Circuits, 2022
Sci. China Inf. Sci., 2022
An improved Monte Carlo localization using optimized iterative closest point for mobile robots.
Cogn. Comput. Syst., 2022
Proceedings of the Digital Multimedia Communications - The 19th International Forum, 2022
A 4.7GHz Synchronized-Multi-Reference PLL with In-Band Phase Noise Lower than Reference Phase Noise +20logN<sub>div</sub>.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
Space-address decoupled scratchpad memory management for neural network accelerators.
Concurr. Comput. Pract. Exp., 2021
A 122-168GHz Radar/Communication Fusion-Mode Transceiver with 30GHz Chirp Bandwidth, 13dBm Psat, and 8.3dBm OP1dB in 28nm CMOS.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A 11.1-to-14.2 GHz Self-adapted Two-point Modulation Dual-path Type-II Digital PLL Concurrently Achieving 124.7-MHz/μs Chirp Rate and 2.27-GHz Bandwidth.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the IMMS 2021: 4th International Conference on Information Management and Management Science, Chengdu, China, August 27, 2021
An 8.2-to-21.5 GHz Dual-Core Quad-Mode Orthogonal-Coupled VCO with Concurrently Dual-Output using Parallel 8-Shaped Resonator.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
A Fully Integrated K-Band Dual Down-Conversion Receiver for Radar Applications in 90 nm CMOS.
IEEE Access, 2020
A Highly-Integrated Ka-Band Direct Up-Conversion Transmitter for Satellite Communication in 65nm CMOS.
Proceedings of the 20th IEEE International Conference on Communication Technology, 2020
2019
A Fully Integrated 27.5-30.5 GHz 8-Element Phased-Array Transmit Front-end Module in 65 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2012
Proceedings of the Fifth International Joint Conference on Computational Sciences and Optimization, 2012
2009
Proceedings of the Advances in Computation and Intelligence, 4th International Symposium, 2009
Proceedings of the Sixth International Conference on Fuzzy Systems and Knowledge Discovery, 2009
2007
Research on Inferring ELECTRE-III's Parameters with Fuzzy Information and a Case on Naval Gun Weapon System Integration.
Proceedings of the Fourth International Conference on Fuzzy Systems and Knowledge Discovery, 2007