Hoyeol Cho

According to our database, Hoyeol Cho authored at least 6 papers between 2007 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of two.

2016

SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor.

Georgios K. Konstadinidis, Hongping Penny Li, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister, Jeffrey Brooks, Ha Pham, Sebastian Turullols, Yifan YangGong, Robert T. Golla, Alan P. Smith, Ali Vahidsafa

IEEE J. Solid State Circuits, 2016

2015

4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor.

Penny Li, Jinuk Luke Shin, Georgios K. Konstadinidis, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm.

Jason Hart, Hoyeol Cho, Yuefei Ge, Gregory Gruber, Dawei Huang, Changku Hwang, Daisy Jian, Timothy Johnson, Georgios K. Konstadinidis, Venkatram Krishnaswamy, Lance Kwong, Robert P. Masleid, Rakesh Mehta, Umesh Nawathe, Aparna Ramachandran, Harikaran Sathianathan, Yongning Sheng, Jinuk Luke Shin, Sebastian Turullols, Zuxu Qin, King C. Yen

IEEE J. Solid State Circuits, 2014

2013

3.6GHz 16-core SPARC SoC processor in 28nm.

Jason Hart, Steve Butler, Hoyeol Cho, Yuefei Ge, Gregory Gruber, Dawei Huang, Changku Hwang, Daisy Jian, Timothy Johnson, Georgios K. Konstadinidis, Lance Kwong, Robert P. Masleid, Umesh Nawathe, Aparna Ramachandran, Yongning Sheng, Jinuk Luke Shin, Sebastian Turullols, Zuxu Qin, King C. Yen

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2008

Performance comparison between copper, carbon nanotube, and optical interconnects.

Krishna Saraswat, Hoyeol Cho, Pawan Kapur, Kyung-Hoae Koo

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

Modeling of the performance of carbon nanotube bundle, cu/low-k and optical on-chip global interconnects.

Hoyeol Cho, Kyung-Hoae Koo, Pawan Kapur, Krishna Saraswat

Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007