Heechoul Park

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.

Bibliography

2016

SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2016

2015

4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor.

[BibT_eX]

[DOI]

Penny Li

Jinuk Luke Shin

Georgios K. Konstadinidis

Francis Schumacher

Venkatram Krishnaswamy

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2013

The Next Generation 64b SPARC Core in a T4 SoC Processor.

[BibT_eX]

[DOI]

Harikaran Sathianathan

Georgios K. Konstadinidis

Mary Jo Doherty

Greg Grohoski

Curtis McAllister

IEEE J. Solid State Circuits, 2013

2012

The next-generation 64b SPARC core in a T4 SoC processor.

[BibT_eX]

[DOI]

Harikaran Sathianathan

Georgios K. Konstadinidis

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2007

An 8-Core 64-Thread 64b Power-Efficient SPARC SoC.

[BibT_eX]

[DOI]

Umesh Gajanan Nawathe

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005

A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2005

Heechoul Park

Bibliography

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