Ha Pham

According to our database1, Ha Pham authored at least 15 papers between 2005 and 2024.

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Bibliography

2024
Numerical investigation of stabilization in the Hybridizable Discontinuous Galerkin method for linear anisotropic elastic equation.
CoRR, 2024

2023
Harvesting tomatoes with a Robot: an evaluation of Computer-Vision capabilities.
Proceedings of the IEEE International Conference on Autonomous Robot Systems and Competitions, 2023

2022
Using proposed optimization algorithm for solving inverse kinematics of human upper limb applying in rehabilitation robotic.
Artif. Intell. Rev., 2022

Disparities in Patient Portal Use in Radiotherapy Treated Patients in the Era of COVID-19.
Proceedings of the AMIA 2022, 2022

2021
Simulation and Experiment in Solving Inverse Kinematic for Human Upper Limb by Using Optimization Algorithm.
Proceedings of the Intelligent Information and Database Systems - 13th Asian Conference, 2021

2020
Efficient and Accurate Algorithm for the Full Modal Green's Kernel of the Scalar Wave Equation in Helioseismology.
SIAM J. Appl. Math., 2020

2019
Champs et objets pour mieux représenter les phénomènes dans leur contexte géographique.
Rev. Int. Géomatique, 2019

Energy Cost Optimization in Microgrids Using Model Predictive Control and Mixed Integer Linear Programming.
Proceedings of the IEEE International Conference on Industrial Technology, 2019

2018
Localization of small obstacles from back-scattered data at limited incident angles with full-waveform inversion.
J. Comput. Phys., 2018

2016
SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor.
IEEE J. Solid State Circuits, 2016

2015
Representing Urban Phenomena in Their Context and at Different LoD: from Raw Data to Appropriate LoD.
Proceedings of the Eurographics Workshop on Urban Data Modelling and Visualisation, 2015

4.3 Fine-grained adaptive power management of the SPARC M7 processor.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2011
A 40 nm 16-Core 128-Thread SPARC SoC Processor.
IEEE J. Solid State Circuits, 2011

2010
A 40nm 16-core 128-thread CMT SPARC SoC processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2005
A dual-core 64-bit ultraSPARC microprocessor for dense server applications.
IEEE J. Solid State Circuits, 2005


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