Huaide Wang

According to our database, Huaide Wang authored at least 13 papers between 2007 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

RC-SLAM: Road Constrained Stereo Visual SLAM System Based on Graph Optimization.

Yuan Zhu, Hao An, Huaide Wang, Ruidong Xu, Mingzhi Wu, Ke Lu

Sensors, January, 2024

2023

DPC-SLAM: Discrete Plane Constrained VSLAM for Intelligent Vehicle in Road Environment.

Zhihong Wu, Huaide Wang, Hao An, Yuan Zhu, Ruidong Xu, Ke Lu

Proceedings of the 25th IEEE International Conference on Intelligent Transportation Systems, 2023

A Visual-Inertial Fusion Mapping and Localization System Using AprilTag in GNSS-Denied Scenes.

Zhihong Wu, Hao An, Boyu Wu, Huaide Wang, Ke Lu

Proceedings of the Intelligent Robotics and Applications - 16th International Conference, 2023

2014

A 4K×2K@60fps multi-standard TV SoC processor with integrated HDMI/MHL receiver.

Chi-Cheng Ju, Tsu-Ming Liu, Huaide Wang, Yung-Chang Chang, Chih-Ming Wang, Chang-Lin Hsieh, Brian Liu, Hue-Min Lin, Chia-Yun Cheng, Chun-Chia Chen, Min-Hao Chiu, Sheng-Jen Wang, Ping Chao, Meng-Jye Hu, Ryan Yeh, Ted Chuang, Hsiu-Yi Lin, Chung-Hung Tsai

Proceedings of the Symposium on VLSI Circuits, 2014

2011

W-Band BPSK and QPSK Transceivers With Costas-Loop Carrier Recovery in 65-nm CMOS Technology.

Shih-Jou Huang, Yu-Ching Yeh, Huaide Wang, Pang-Ning Chen, Jri Lee

IEEE J. Solid State Circuits, 2011

An 87GHz QPSK transceiver with costas-loop carrier recovery in 65nm CMOS.

Shih-Jou Huang, Yu-Ching Yeh, Huaide Wang, Pang-Ning Chen, Jri Lee

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology.

Huaide Wang, Jri Lee

IEEE J. Solid State Circuits, 2010

2009

Study of Subharmonically Injection-Locked PLLs.

Jri Lee, Huaide Wang

IEEE J. Solid State Circuits, 2009

Subharmonically injection-locked PLLs for ultra-low-noise clock generation.

Jri Lee, Huaide Wang, Wen-Tsao Chen, Yung-Pin Lee

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008

A 75-GHz Phase-Locked Loop in 90-nm CMOS Technology.

Jri Lee, Mingchung Liu, Huaide Wang

IEEE J. Solid State Circuits, 2008

Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data.

Jri Lee, Ming-Shuan Chen, Huaide Wang

IEEE J. Solid State Circuits, 2008

A 20Gb/s Duobinary Transceiver in 90nm CMOS.

Jri Lee, Ming-Shuan Chen, Huaide Wang

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

A 20Gb/s Broadband Transmitter with Auto-Configuration Technique.

Jri Lee, Huaide Wang

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007