Huaide Wang

According to our database1, Huaide Wang authored at least 10 papers between 2007 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2014
A 4K×2K@60fps multi-standard TV SoC processor with integrated HDMI/MHL receiver.
Proceedings of the Symposium on VLSI Circuits, 2014

2011
W-Band BPSK and QPSK Transceivers With Costas-Loop Carrier Recovery in 65-nm CMOS Technology.
IEEE J. Solid State Circuits, 2011

An 87GHz QPSK transceiver with costas-loop carrier recovery in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology.
IEEE J. Solid State Circuits, 2010

2009
Study of Subharmonically Injection-Locked PLLs.
IEEE J. Solid State Circuits, 2009

Subharmonically injection-locked PLLs for ultra-low-noise clock generation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
A 75-GHz Phase-Locked Loop in 90-nm CMOS Technology.
IEEE J. Solid State Circuits, 2008

Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data.
IEEE J. Solid State Circuits, 2008

A 20Gb/s Duobinary Transceiver in 90nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
A 20Gb/s Broadband Transmitter with Auto-Configuration Technique.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007


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