Huandong Wang

According to our database1, Huandong Wang
  • authored at least 25 papers between 2009 and 2018.
  • has a "Dijkstra number"2 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
Data-Driven Packet Loss Estimation for Node Healthy Sensing in Decentralized Cluster.
Sensors, 2018

2017
Understanding Mobile Traffic Patterns of Large Scale Cellular Towers in Urban Environment.
IEEE/ACM Trans. Netw., 2017

The complexity of problems in wireless communication.
Telecommunication Systems, 2017

Predictability and Prediction of Human Mobility Based on Application-Collected Location Data.
Proceedings of the 14th IEEE International Conference on Mobile Ad Hoc and Sensor Systems, 2017

From Fingerprint to Footprint: Revealing Physical World Privacy Leakage by Cyberspace Cookie Logs.
Proceedings of the 2017 ACM on Conference on Information and Knowledge Management, 2017

2016
Saving Energy in Partially Deployed Software Defined Networks.
IEEE Trans. Computers, 2016

Leveraging software-defined networking for security policy enforcement.
Inf. Sci., 2016

Multiple-combinational-channel: A network architecture for workload balance and deadlock free.
Future Generation Comp. Syst., 2016

Co-location social networks: Linking the physical world and cyberspace.
Proceedings of the 2016 IEEE/ACM International Conference on Advances in Social Networks Analysis and Mining, 2016

2015
Understanding Mobile Traffic Patterns of Large Scale Cellular Towers in Urban Environment.
CoRR, 2015

Characterizing the Spatio-Temporal Inhomogeneity of Mobile Traffic in Large-scale Cellular Data Networks.
Proceedings of the 7th International Workshop on Hot Topics in Planet-scale mObile computing and online Social neTworking, 2015

Virtual machine migration planning in software-defined networks.
Proceedings of the 2015 IEEE Conference on Computer Communications, 2015

Understanding Mobile Traffic Patterns of Large Scale Cellular Towers in Urban Environment.
Proceedings of the 2015 ACM Internet Measurement Conference, 2015

MRP: mix real cores and pseudo cores for FPGA-based chip-multiprocessor simulation.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
An 8-Core MIPS-Compatible Processor in 32/28 nm Bulk CMOS.
J. Solid-State Circuits, 2014

Virtual Machine Migration Planning in Software-Defined Networks.
CoRR, 2014

2013
An Optimized Solution for Cross-Domain System Bus Transaction Processing.
Proceedings of the 14th ACIS International Conference on Software Engineering, 2013

Godson-3B1500: A 32nm 1.35GHz 40W 172.8GFLOPS 8-core processor.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
Fair Memory Access Scheduling for Quality of Service Guarantees via Service Curves.
Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012

Heterogeneous multi-channel: fine-grained DRAM control for both system performance and power efficiency.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

MCC: A Load Balancing and Deadlock Free Interconnect Network for Cache Coherent Chip Multiprocessors.
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

2011
RIRI scheme: A robust instant-responding ratiochronous interface with zero-latency penalty.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
System Architecture of Godson-3 Multi-Core Processors.
J. Comput. Sci. Technol., 2010

A multi-FPGA based platform for emulating a 100m-transistor-scale processor with high-speed peripherals (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2009
An Enhanced HyperTransport Controller with Cache Coherence Support for Multiple-CMP.
Proceedings of the International Conference on Networking, Architecture, and Storage, 2009


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