Dong Tong

Orcid: 0000-0003-0987-6351

Affiliations:

Peking University, Microprocessor Research and Development Center, Beijing, China

According to our database¹, Dong Tong authored at least 37 papers between 2005 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

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In proceedings

Article

PhD thesis

Dataset

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Bibliography

2023

FlexPointer: Fast Address Translation Based on Range TLB and Tagged Pointers.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., June, 2023

2021

MetaTableLite: An Efficient Metadata Management Scheme for Tagged-Pointer-Based Spatial Safety.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Prediction of Register Instance Usage and Time-sharing Register for Extended Register Reuse Scheme.

[BibT_eX]

[DOI]

Shuxin Zhou

Huandong Wang

Dong Tong

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

S3Library: Automatically Eliminating C/C++ Buffer Overflow using Compatible Safer Libraries.

[BibT_eX]

[DOI]

CoRR, 2020

DangKiller: Eliminating Dangling Pointers Efficiently via Implicit Identifier.

[BibT_eX]

[DOI]

CoRR, 2020

SMA: Eliminate Memory Spatial Errors via Saturation Memory Access.

[BibT_eX]

[DOI]

CoRR, 2020

2017

Locality-aware bank partitioning for shared DRAM MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

A Staged Memory Resource Management Method for CMP systems.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016

MFAP: Fair Allocation between fully backlogged and non-fully backlogged applications.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2014

A General Low-Cost Indirect Branch Prediction Using Target Address Pointers.

[BibT_eX]

[DOI]

Zichao Xie

Dong Tong

Mingkai Huang

J. Comput. Sci. Technol., 2014

Improving system throughput and fairness simultaneously in shared memory CMP systems via Dynamic Bank Partitioning.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013

SPIRE: improving dynamic binary translation through SPC-indexed indirect branch redirecting.

[BibT_eX]

[DOI]

Proceedings of the ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (co-located with ASPLOS 2013), 2013

Page policy control with memory partitioning for DRAM performance and power efficiency.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

An energy-efficient branch prediction technique via global-history noise reduction.

[BibT_eX]

[DOI]

Zichao Xie

Dong Tong

Xu Cheng

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

VFCC: A verification framework of cache coherence using parallel simulation.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

An adaptive filtering mechanism for energy efficient data prefetching.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Active Store Window: Enabling Far Store-Load Forwarding with Scalability and Complexity-Efficiency.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2012

SWIP Prediction: Complexity-Effective Indirect-Branch Prediction Using Pointers.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2012

SOLE: Speculative one-cycle load execution with scalability, high-performance and energy-efficiency.

[BibT_eX]

[DOI]

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Improving inclusive cache performance with two-level eviction priority.

[BibT_eX]

[DOI]

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Energy-efficient branch prediction with Compiler-guided History Stack.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

S/DC: A storage and energy efficient data prefetcher.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Optimal bypass monitor for high performance last-level caches.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011

CGA: Combining cluster analysis with genetic algorithm for regression suite reduction of microprocessors.

[BibT_eX]

[DOI]

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

TAP prediction: Reusing conditional branch predictor for indirect branches with Target Address Pointers.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2010

Research Progress of UniCore CPUs and PKUnity SoCs.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2010

TERA: A FPGA-based trace-driven emulation framework for designing on-chip communication architectures.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Energy efficient management scheme for heterogeneous secondary storage system in mobile computers.

[BibT_eX]

[DOI]

Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), 2010

FPGA prototyping of an amba-based windows-compatible SoC.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

FEMU: a firmware-based emulation framework for SoC verification.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

2009

WHOLE: A low energy I-Cache with separate way history.

[BibT_eX]

[DOI]

Zichao Xie

Dong Tong

Xu Cheng

Proceedings of the 27th International Conference on Computer Design, 2009

Track Down HW Function Faults Using Real SW Invariants.

[BibT_eX]

[DOI]

Proceedings of the CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31, 2009

2008

CASA: A New IFU Architecture for Power-Efficient Instruction Cache and TLB Designs.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2008

2007

An Energy-Efficient Instruction Scheduler Design with Two-Level Shelving and Adaptive Banking.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2007

Reuse Distance Based Cache Leakage Control.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing, 2007

Clock domain crossing fault model and coverage metric for validation of SoC design.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2005

Non-interleaving architecture for hardware implementation of modular multiplication.

[BibT_eX]

[DOI]

Qiang Liu

Dong Tong

Xu Cheng

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Dong Tong

Timeline

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