Hungse Cha

According to our database, Hungse Cha authored at least 5 papers between 1993 and 1996.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

1996

A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults.

Hungse Cha, Elizabeth M. Rudnick, Janak H. Patel, Ravishankar K. Iyer, Gwan S. Choi

IEEE Trans. Computers, 1996

1994

Latch Design for Transient Pulse Tolerance.

Hungse Cha, Janak H. Patel

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Fast timing simulation of transient faults in digital circuits.

Abhijit Dharchoudhury, Sung-Mo Kang, Hungse Cha, Janak H. Patel

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993

A Logic-Level Model for alpha-Paricle Hits in CMOS Circuits.

Hungse Cha, Janak H. Patel

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

A Fast and Accurate Gate-Level Transient Fault Simulation Environment.

Hungse Cha, Elizabeth M. Rudnick, Gwan S. Choi, Janak H. Patel, Ravishankar K. Iyer

Proceedings of the Digest of Papers: FTCS-23, 1993