Abhijit Dharchoudhury

According to our database1, Abhijit Dharchoudhury authored at least 16 papers between 1992 and 1999.

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Bibliography

1999
Timing and Signal Integrity Analysis.
Proceedings of the VLSI Handbook., 1999

A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Emerging power management tools for processor design.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

CMOS Combinational Circuit Sizing by Stage-wise Tapering.
Proceedings of the 1998 Design, 1998

Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization.
Proceedings of the 35th Conference on Design Automation, 1998

Design and Analysis of Power Distribution Networks in PowerPC Microprocessors.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Library-less synthesis for static CMOS combinational logic circuits.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996
iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Worst-case analysis and optimization of VLSI circuit performances.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

1994
Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Fast timing simulation of transient faults in digital circuits.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993
Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
Identification of Correlated Device Model Parameter Values for Worst-Case Circuit Performance Analysis.
Proceedings of the Fifth International Conference on VLSI Design, 1992

An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog Circuits.
Proceedings of the 29th Design Automation Conference, 1992


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