Elizabeth M. Rudnick

According to our database1, Elizabeth M. Rudnick authored at least 61 papers between 1991 and 2004.

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Bibliography

2004
Automatic Generation of Diagnostic Memory Tests Based on Fault Decomposition and Output Tracing.
IEEE Trans. Computers, 2004

2003
A data acquisition methodology for on-chip repair of embedded memories.
ACM Trans. Design Autom. Electr. Syst., 2003

2002
A Genetic Testing Framework for Digital Integrated Circuits.
Proceedings of the 14th IEEE International Conference on Tools with Artificial Intelligence (ICTAI 2002), 2002

Functional Test Generation For Digital Integrated Circuits Using A Genetic Algorithm.
Proceedings of the GECCO 2002: Proceedings of the Genetic and Evolutionary Computation Conference, 2002

Low-cost sequential ATPG with clock-control DFT.
Proceedings of the 39th Design Automation Conference, 2002

2001
Diagnostic simulation of stuck-at faults in sequential circuits using compact lists.
ACM Trans. Design Autom. Electr. Syst., 2001

Use of a field programmable gate array for education in manufacturing test and automatic test equipment.
IEEE Trans. Education, 2001

Sequential Circuit Test Generation Using a Symbolic/Genetic Hybrid Approach.
J. Electronic Testing, 2001

Automatic Generation of Diagnostic March Tests.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

At-speed logic BIST using a frozen clock testing strategy.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

2000
Peak power estimation of VLSI circuits: new peak power measures.
IEEE Trans. VLSI Syst., 2000

Dynamic state traversal for sequential circuit test generation.
ACM Trans. Design Autom. Electr. Syst., 2000

Bridge fault diagnosis using stuck-at fault simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Compact Test Generation Using a Frozen Clock Testing Strategy.
J. Inf. Sci. Eng., 2000

A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors.
J. Electronic Testing, 2000

Diagnostic Testing of Embedded Memories Based on Output Tracing.
Proceedings of the 8th IEEE International Workshop on Memory Technology, 2000

Diagnostic test generation for sequential circuits.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Diagnostic Testing of Embedded Memories Using BIST.
Proceedings of the 2000 Design, 2000

1999
Microprocessor Design Verification.
Proceedings of the VLSI Handbook., 1999

Efficient Techniques for Dynamic Test Sequence Compaction.
IEEE Trans. Computers, 1999

Fast Static Compaction Algorithms for Sequential Circuit Test Vectors.
IEEE Trans. Computers, 1999

A Diagnostic Fault Simulator for Fast Diagnosis of Bridge Faults.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

A Fault List Reduction Approach for Efficient Bridge Fault Diagnosis.
Proceedings of the 1999 Design, 1999

FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy.
Proceedings of the 1999 Design, 1999

1998
Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Partial Scan Selection Based on Dynamic Reachability and Observability Information.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Enhancing topological ATPG with high-level information and symbolic techniques.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques.
Proceedings of the 1998 Design, 1998

1997
A genetic algorithm framework for test generation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Static logic implication with application to redundancy identification.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Dynamic Fault Grouping for PROOFS: A Win for Large Sequential Circuits.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Asynchronous Parallel Algorithms for Test Set Partitioned Fault Simulation.
Proceedings of the Eleventh Workshop on Parallel and Distributed Simulation, 1997

Putting the Squeeze on Test Sequences.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

K2: an estimator for peak sustainable power of VLSI circuits.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Effects of delay models on peak power estimation of VLSI sequential circuits.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Sequential circuit test generation using dynamic state traversal.
Proceedings of the European Design and Test Conference, 1997

1996
A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults.
IEEE Trans. Computers, 1996

Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Automatic test generation using genetically-engineered distinguishing sequences.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

On Potential Fault Detection in Sequential Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Testability Insertion in Behavioral Descriptions.
Proceedings of the 9th International Symposium on System Synthesis, 1996

Simulation-based techniques for dynamic test sequence compaction.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Enhancing high-level control-flow for improved testability.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Alternating Strategies for Sequential Circuit ATPG.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Sequential circuit testability enhancement using a nonscan approach.
IEEE Trans. VLSI Syst., 1995

A genetic approach to test application time reduction for full scan and partial scan circuits.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists.
Proceedings of the 32st Conference on Design Automation, 1995

Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation.
Proceedings of the 32st Conference on Design Automation, 1995

1994
An observability enhancement approach for improved testability and at-speed test.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

Application of Simple Genetic Algorithms to Sequential Circuit Test Generation.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Sequential Circuit Test Generation in a Genetic Algorithm Framework.
Proceedings of the 31st Conference on Design Automation, 1994

1993
A Fast and Accurate Gate-Level Transient Fault Simulation Environment.
Proceedings of the Digest of Papers: FTCS-23, 1993

Non-Scan Design-for-Testability Techniques for Sequential Circuits.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
Probe point insertion for at-speed test.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Diagnostic Fault Simulation of Sequential Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991
Methods for Reducing Events in Sequential Circuit Fault Simulation.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991


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