Hyoung-Jung Kim

According to our database, Hyoung-Jung Kim authored at least 5 papers between 2022 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2026

A Hybrid Voltage-Time Domain Pipelined ADC With Reference-Embedded Time-Domain Residues.

Jae-Geun Lim, Jun-Ho Boo, Jae-Hyuk Lee, Hyoung-Jung Kim, Byeongho Yu, Kang-Il Cho, Sungho Lee, Un-Ku Moon, Gil-Cho Ahn

IEEE J. Solid State Circuits, February, 2026

2025

A Two-Step ADC with a Separate DAC Method for Enhanced Sub-Quantizer Settling Condition.

Jae-Geun Lim, Jun-Ho Boo, Hyoung-Jung Kim, Jae-Hyuk Lee, Kang-Il Cho, Gil-Cho Ahn

Proceedings of the International Conference on Electronics, Information, and Communication, 2025

2023

A Second-Order DT Delta-Sigma Modulator with Noise-Shaping SAR Quantizer.

Seong-Bo Park, Jun-Ho Boo, Jae-Geun Lim, Hyoung-Jung Kim, Jae-Hyuk Lee, Won-Jun Cho, Gil-Cho Ahn

Proceedings of the 20th International SoC Design Conference, 2023

A 12-bit 3-MS/s Synchronous SAR ADC With a Hybrid RC DAC.

Mi-Ji Go, Jun-Ho Boo, Jae-Geun Lim, Hyoung-Jung Kim, Jae-Hyuk Lee, Seong-Bo Park, Byeongho Yu, Won-Jun Cho, Gil-Cho Ahn

Proceedings of the 20th International SoC Design Conference, 2023

2022

A 430-MS/s 7-b Asynchronous SAR ADC With a 40 fF Input Sampling Capacitor.

Hyoung-Jung Kim, Jae-Hyuk Lee, Jae-Geun Lim, Jun-Ho Boo, Ho-Jin Kim, Seong-Bo Park, Youngdon Choi, Jung-Hwan Choi, Gil-Cho Ahn

Proceedings of the 19th International SoC Design Conference, 2022