Jun-Ho Boo

Orcid: 0000-0002-6139-4459

According to our database1, Jun-Ho Boo authored at least 13 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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Links

On csauthors.net:

Bibliography

2024
A CMOS Analog Front-End for Hall Sensor Readout IC.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024

2023
A Single-Loop Third-Order 10-MHz BW Source-Follower-Integrator Based Discrete-Time Delta-Sigma ADC.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023

A Second-Order DT Delta-Sigma Modulator with Noise-Shaping SAR Quantizer.
Proceedings of the 20th International SoC Design Conference, 2023

A 12-bit 3-MS/s Synchronous SAR ADC With a Hybrid RC DAC.
Proceedings of the 20th International SoC Design Conference, 2023

2022
A 430-MS/s 7-b Asynchronous SAR ADC With a 40 fF Input Sampling Capacitor.
Proceedings of the 19th International SoC Design Conference, 2022

2021
A 96dB Dynamic Range 2kHz Bandwidth 2nd Order Delta-Sigma Modulator Using Modified Feed-Forward Architecture With Delayed Feedback.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, -0.12% for Battery-Monitoring Applications.
IEEE J. Solid State Circuits, 2021

A 0.9V 0.022mm<sup>2</sup> 103dB DR Switched-Capacitor Audio Delta-Sigma Modulator Using Input-Referred kT/C Noise Reduction Technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
A Third-Order DT Delta-Sigma Modulator With Noise-Coupling Technique.
Proceedings of the International SoC Design Conference, 2020

A 2.2mW 12-bit 200MS/s 28nm CMOS Pipelined SAR ADC with Dynamic Register-Based High-Speed SAR Logic.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020

A 10-b 900-MS/s Single-Channel Pipelined-SAR ADC Using Current-Mode Reference Scaling.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020

2019
A 101 dB Dynamic Range Delta-Sigma Modulator Using Modified Feed-Forward Architecture for Audio Application.
Proceedings of the 2019 International SoC Design Conference, 2019

A 10-b 320-MS/s Dual-Residue Pipelined SAR ADC with Binary Search Current Interpolator.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019


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