Hyoungjoong Kim
According to our database1,
Hyoungjoong Kim
authored at least 4 papers
between 2009 and 2024.
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Collaborative distances:
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Bibliography
2024
A 0.036mm<sup>2</sup> 80Mb/s-to-15.96Gb/s C-PHY and D-PHY Combo Receiver with Background Calibrations in 4nm FinFET.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
2022
A 64Gb/s Downlink and 32Gb/s Uplink NRZ Wireline Transceiver with Supply Regulation, Background Clock Correction and EOM-based Channel Adaptation for Mid-Reach Cellular Mobile Interface in 8nm FinFET.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2020
22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2009
IEEE Trans. Circuits Syst. II Express Briefs, 2009