Jongshin Shin
Orcid: 0000-0002-4912-4974
According to our database1,
Jongshin Shin
authored at least 35 papers
between 2000 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection.
IEEE J. Solid State Circuits, January, 2024
13.10 A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
3.9 A 1.2V High-Voltage-Tolerant Bootstrapped Analog Sampler in 12-bit SAR ADC Using 3nm GAA's 0.7V Thin-Gate-Oxide Transistor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links.
IEEE J. Solid State Circuits, 2023
IEEE Access, 2023
A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 12-bit 8GS/s RF Sampling DAC with Code-Dependent Nonlinearity Compensation and Intersegmental Current-Mismatch Calibration in 5nm FinFET.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 0.65V 1316µm<sup>2</sup>Fully Synthesizable Digital Temperature Sensor Using Wire Metal Achieving O.16nJ.%2-Accuracy FoM in 5nm FinFET CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Clock Generator with IS026262 ASIL-D Grade Safety Mechanism for SoC Clocking Application.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A Hybrid Always-Dual-Path Recursive Step-Down Converter Using Adaptive Switching Level Control Achieving 95.4% Efficiency with 288mΩ Large-DCR Inductor.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
29.6 A Distributed Digital LDO with Time-Multiplexing Calibration Loop Achieving 40A/mm2 Current Density and 1mA-to-6.4A Ultra-Wide Load Range in 5nm FinFET CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 12b 600MS/s Pipelined SAR and 2x-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFET.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Samsung Physically Unclonable Function (SAMPUF™) and its integration with Samsung Security System.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
An 18-Gb/s NRZ Transceiver With a Channel-Included 2-UI Impulse-Response Filtering FFE and 1-Tap DFE Compensating up to 32-dB Loss.
IEEE Trans. Circuits Syst., 2020
IEEE J. Solid State Circuits, 2020
6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
11.8 A 96.8%-Efficiency Continuous Input/Output-Current Step-Up/Down Converter Powering Disposable IoTs with Reconfigurable Multi-Cell-Balanced Alkaline Batteries.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2018
Proceedings of the International SoC Design Conference, 2018
2016
A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
2013
A tracked oversampling digital data recovery for Low Latency, fast acquisition, and high jitter tolerance.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
2009
IEICE Electron. Express, 2009
2008
A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2006
A Low-Jitter Added SSCG with Seamless Phase Selection and Fast AFC for 3rd Generation Serial-ATA.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2001
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001
A genetic approach to automatic bias generation for biased random instruction generation.
Proceedings of the 2001 Congress on Evolutionary Computation, 2001
2000
A new charge pump without degradation in threshold voltage due to body effect [memory applications].
IEEE J. Solid State Circuits, 2000