Hyunsu Chae

Orcid: 0000-0001-9266-555X

According to our database1, Hyunsu Chae authored at least 8 papers between 2004 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
ISOP+: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024

A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization.
IEEE J. Solid State Circuits, January, 2024

2023
A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022
A 64Gb/s Downlink and 32Gb/s Uplink NRZ Wireline Transceiver with Supply Regulation, Background Clock Correction and EOM-based Channel Adaptation for Mid-Reach Cellular Mobile Interface in 8nm FinFET.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2018
Test cost reduction for <i>X</i>-value elimination by scan slice correlation analysis.
Proceedings of the 55th Annual Design Automation Conference, 2018

2005
A Fast Hopping Frequency Synthesizer for UWB Systems in a CMOS Technology.
Proceedings of the 2nd IEEE International Symposium on Wireless Communication Systems, 2005

2004
High speed mixed analog/digital PRML architecture for optical data storage system.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

An improved architecture of the mixed mode clock/data recovery for DVD read channel.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004


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