I-Lun Tseng

According to our database, I-Lun Tseng authored at least 19 papers between 2004 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Challenges in Floorplanning and Macro Placement for Modern SoCs.

I-Lun Tseng

Proceedings of the 2024 International Symposium on Physical Design, 2024

2022

Flexible Multiple-Objective Reinforcement Learning for Chip Placement.

Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen

CoRR, 2022

Flexible chip placement via reinforcement learning: late breaking results.

Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2019

A System for Standard Cell Routability Checking and Placement Routability Improvements.

I-Lun Tseng, Zhao Chuan Lee, Vikas Tripathi, Chun Ming Tommy Yip, Zhinan Chen, Jonathan Ong

Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2018

Context-Aware DFM Rule Analysis and Scoring Using Machine Learning.

Vikas Tripathi, Valerio Perez, Yongfu Li, Zhao Chuan Lee, I-Lun Tseng, Jonathan Ong

CoRR, 2018

Creation and Fixing of Lithography Hotspots with Synopsys Tools.

I-Lun Tseng, Valerio Perez, Yongfu Li, Zhao Chuan Lee, Vikas Tripathi, Yoong Seang Jonathan Ong

CoRR, 2018

Advanced In-Design Auto-Fixing Flow for Cell Abutment Pattern Matching Weakpoints.

Yongfu Li, Valerio Perez, I-Lun Tseng, Zhao Chuan Lee, Vikas Tripathi, Jason Khaw, Yoong Seang Jonathan Ong

CoRR, 2018

In Design DFM Rule Scoring and Fixing Method using ICV.

Vikas Tripathi, Yongfu Li, Zhao Chuan Lee, I-Lun Tseng, Jason Khaw, Jonathan Ong

CoRR, 2018

Identifying Lithography Weak-Points of Standard Cells with Partial Pattern Matching.

Yongfu Li, I-Lun Tseng, Zhao Chuan Lee, Valerio Perez, Vikas Tripathi, Yoong Seang Jonathan Ong

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

An Automated System for Checking Lithography Friendliness of Standard Cells.

I-Lun Tseng, Yongfu Li, Valerio Perez, Vikas Tripathi, Zhao Chuan Lee, Yoong Seang Jonathan Ong

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2013

A parallel dual-scanline algorithm for partitioning parameterized 45-degree polygons.

Yao-Lin Chang, I-Lun Tseng

ACM Trans. Design Autom. Electr. Syst., 2013

Fast partitioning of parameterized 45-degree polygons into parameterized trapezoids.

Yao-I Tseng, I-Lun Tseng, Tsao Hsiao Huang, Adam Postula

Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Boolean mask operations on parameterized 45-degree polygons.

Yao-I Tseng, I-Lun Tseng, Adam Postula

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Relocatable and resizable SRAM synthesis for via configurable structured ASIC.

Hsin-Hung Liu, Rung-Bin Lin, I-Lun Tseng

Proceedings of the International Symposium on Quality Electronic Design, 2013

2010

Constraint-Based Dogleg Channel Routing with Via Minimization.

I-Lun Tseng, Huan-Wen Chen, Che-I Lee, Adam Postula

Proceedings of the 2010 International Conference on Artificial Intelligence, 2010

2008

Estimation of Analog Layout Parasitics with Parameterized Polygons

I-Lun Tseng

PhD thesis, 2008

Partitioning parameterized 45-degree polygons with constraint programming.

I-Lun Tseng, Adam Postula

ACM Trans. Design Autom. Electr. Syst., 2008

2006

An efficient algorithm for partitioning parameterized polygons into rectangles.

I-Lun Tseng, Adam Postula

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

2004

GBLD: A Formal Model for Layout Description and Generation.

I-Lun Tseng, Adam Postula

Proceedings of the Forum on specification and Design Languages, 2004