Zhao Chuan Lee

According to our database1, Zhao Chuan Lee authored at least 18 papers between 2012 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

On csauthors.net:

Bibliography

2021
A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI.
IEEE Trans. Very Large Scale Integr. Syst., 2021

2019
Improving uniformity and reliability of SRAM PUFs utilizing device aging phenomenon for unique identifier generation.
Microelectron. J., 2019

An 8T SRAM With On-Chip Dynamic Reliability Management and Two-Phase Write Operation in 28-nm FDSOI.
IEEE J. Solid State Circuits, 2019

A System for Standard Cell Routability Checking and Placement Routability Improvements.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2018
Context-Aware DFM Rule Analysis and Scoring Using Machine Learning.
CoRR, 2018

Creation and Fixing of Lithography Hotspots with Synopsys Tools.
CoRR, 2018

Advanced In-Design Auto-Fixing Flow for Cell Abutment Pattern Matching Weakpoints.
CoRR, 2018

In Design DFM Rule Scoring and Fixing Method using ICV.
CoRR, 2018

Identifying Lithography Weak-Points of Standard Cells with Partial Pattern Matching.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

An Automated System for Checking Lithography Friendliness of Standard Cells.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
A 16kb column-based split cell-VSS, data-aware write-assisted 9T ultra-low voltage SRAM with enhanced read sensing margin in 28nm FDSOI.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization.
IEEE J. Solid State Circuits, 2016

An 8T SRAM with BTI-Aware Stability Monitor and two-phase write operation for cell stability improvement in 28-nm FDSOI.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2014
0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation Tolerance.
IEEE J. Solid State Circuits, 2014

0.2 V 8T SRAM with improved bitline sensing using column-based data randomization.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
NBTI/PBTI-Aware WWL Voltage Control for Half-Selected Cell Stability Improvement.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

2012
NBTI/PBTI-aware wordline voltage control with no boosted supply for stability improvement of half-selected SRAM cells.
Proceedings of the International SoC Design Conference, 2012

A novel analog-to-residue converter for biomedical DSP application.
Proceedings of the International SoC Design Conference, 2012


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