Ian M. Bell

Affiliations:
  • Department of Engineering, University of Hull, Hull, UK


According to our database1, Ian M. Bell authored at least 18 papers between 1995 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2013
Survey and Evaluation of Automated Model Generation Techniques for High Level Modeling and High Level Fault Modeling.
J. Electron. Test., 2013

2011
Assessment of Microfluidic System Testability using Fault Simulation and Test Metrics.
J. Electron. Test., 2011

2010
Automated Model Generation Algorithm for High-Level Fault Modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2008
A novel approach for automated model generation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Asynchronous arbiter for micro-threaded chip multiprocessors.
J. Syst. Archit., 2007

The Effectiveness of Test in Controlling Quality Costs: A Conformability Analysis Based Approach.
J. Electron. Test., 2007

High Level Modelling and Design For a Microthreaded Scheduler to Support Microgrids.
Proceedings of the 2007 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2007), 2007

2006
Supporting Microthread Scheduling and Synchronisation in CMPs.
Int. J. Parallel Program., 2006

Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors.
Proceedings of the Architecture of Computing Systems, 2006

2004
Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations.
J. Electron. Test., 2004

2002
Design, Manufacture and Test - Quality Test Estimation.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

1998
Evaluation and comparison of structural test methodologies for analogue and mixed signal circuits.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1997
Diagnosis of CMOS op-amps with gate oxide short faults using multilayer perceptrons.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

An On-Line Self-Testing Switched-Current Integrator.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Generation and Verification of Tests for Analogue Circuits Subject to Process Parameter Deviations.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

1996
Mixed current/voltage observation towards effective testing of analog and mixed-signal circuits.
J. Electron. Test., 1996

1995
Concurrent Self Test of Switched Current Circuits Based on the S<sup>2</sup>I-Technique.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Fault Orientated Test and Fault Simulation of Mixed Signal Integrated Circuits.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995


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