Fawnizu Azmadi Hussin

Orcid: 0000-0002-1419-9300

According to our database1, Fawnizu Azmadi Hussin authored at least 48 papers between 2006 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Hybrid Harris Hawks With Sine Cosine for Optimal Node Placement and Congestion Reduction in an Industrial Wireless Mesh Network.
IEEE Access, 2023

2022
An Arithmetic-Trigonometric Optimization Algorithm with Application for Control of Real-Time Pressure Process Plant.
Sensors, 2022

Optimal Coverage and Connectivity in Industrial Wireless Mesh Networks Based on Harris' Hawk Optimization Algorithm.
IEEE Access, 2022

Composite Lightweight Authenticated Encryption Based on LED Block Cipher and PHOTON Hash Function for IoT Devices.
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

An Adaptive Hardware Architecture using Quantized HOG Features for Object Detection.
Proceedings of the International Conference on IC Design and Technology, 2022

2021
A Survey on the Application of WirelessHART for Industrial Process Monitoring and Control.
Sensors, 2021

2-D Design of Double Gate Schottky Tunnel MOSFET for High-Performance Use in Analog/RF Applications.
IEEE Access, 2021

Design and Implementation of Signal Filtering Techniques on Real-time Pressure Process Plant.
Proceedings of the 11th IEEE International Conference on Control System, 2021

Design of Fractional-Order Predictive PI Controller for Real-time Pressure Process Plant <sup>*</sup>.
Proceedings of the 2021 Australian & New Zealand Control Conference, 2021

Reconstruction of Chaotic Attractor for Fractional-order Tamaševičius System Using Recurrent Neural Networks.
Proceedings of the 2021 Australian & New Zealand Control Conference, 2021

2020
Fractional-Order Predictive PI Controller for Dead-Time Processes With Set-Point and Noise Filtering.
IEEE Access, 2020

FPGA-Based Lightweight Hardware Architecture of the PHOTON Hash Function for IoT Edge Devices.
IEEE Access, 2020

2019
Net Classification Based on Testability and Netlist Structural Features for Hardware Trojan Detection.
Proceedings of the 28th IEEE Asian Test Symposium, 2019

Machine-Learning-Based Multiple Abstraction-Level Detection of Hardware Trojan Inserted at Register-Transfer Level.
Proceedings of the 28th IEEE Asian Test Symposium, 2019

2017
Advances in Testing Techniques for Digital Microfluidic Biochips.
Sensors, 2017

A Hybrid Delay Design-for-Testability for Nonseparable RTL Controller-Data Path Circuits.
J. Circuits Syst. Comput., 2017

Bio-inspired fault tolerant network on chip.
Integr., 2017

Offline Error Detection in MEDA-Based Digital Microfluidic Biochips Using Oscillation-Based Testing Methodology.
J. Electron. Test., 2017

Minimizing scheduling overhead in LRE-TL real-time multiprocessor scheduling algorithm.
Turkish J. Electr. Eng. Comput. Sci., 2017

Localization of optic disc and fovea in retinal images using intensity based line scanning analysis.
Comput. Biol. Medicine, 2017

Detection and Classification of Bleeding Region in WCE Images using Color Feature.
Proceedings of the 15th International Workshop on Content-Based Multimedia Indexing, 2017

2016
Bio-inspired NoC fault tolerant techniques using guaranteed throughput and best effort services.
Integr., 2016

Fault Modeling and Simulation of MEDA Based Digital Microfluidics Biochips.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Dual-Engine Cross-ISA DBTO Technique Utilising MultiThreaded Support for Multicore Processor System.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

2015
Resistive Open Faults Detectability Analysis and Implications for Testing Low Power Nanometric ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Implications of Burn-In Stress on NBTI Degradation.
CoRR, 2015

Optimum Colour Space Selection for Ulcerated Regions Using Statistical Analysis and Classification of Ulcerated Frames from WCE Video Footage.
Proceedings of the Neural Information Processing - 22nd International Conference, 2015

2014
Multivoltage Aware Resistive Open Fault Model.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Image Enhancement Using Geometric Mean Filter and Gamma Correction for WCE Images.
Proceedings of the Neural Information Processing - 21st International Conference, 2014

2013
Survey and Evaluation of Automated Model Generation Techniques for High Level Modeling and High Level Fault Modeling.
J. Electron. Test., 2013

USG, an Un-fair, Semi Greedy Optimal Real-Time Multiprocessor Scheduling Algorithm.
Proceedings of the REACTION 2013, 2013

High throughput architecture for low density parity check (LDPC) encoder.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Synaptogenesis based bio-inspired NoC fault tolerant interconnects.
Proceedings of the 2013 IEEE International Conference on Control System, 2013

SEOS: Hardware Implementation of Real-Time Operating System for Adaptability.
Proceedings of the First International Symposium on Computing and Networking, 2013

A Modified LRE-TL Real-Time Multiprocessor Scheduling Algorithm.
Proceedings of the First International Conference on Advanced Data and Information Engineering, 2013

2012
Design for cold test elimination - facing the Inverse Temperature Dependence (ITD) challenge.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Multi-voltage aware resistive open fault modeling.
Proceedings of the 17th IEEE European Test Symposium, 2012

2011
IDVP (Intra-Die Variation Probe) for System-On-Chip (SoC) Infant Mortality screen.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
Optimization of Processor Architecture for Image Edge Detection Filter.
Proceedings of the 12th UKSim, 2010

Space Vector PWM for PMSM simulation using Matlab Simulink.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

RedSOCs-3D: Thermal-safe test scheduling for 3D-stacked SOC.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2008
Scheduling Power-Constrained Tests through the SoC Functional Bus.
IEICE Trans. Inf. Syst., 2008

NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints.
IEICE Trans. Inf. Syst., 2008

On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time.
IEICE Trans. Inf. Syst., 2008

2007
Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints.
Proceedings of the 12th European Test Symposium, 2007

Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing.
Proceedings of the 16th Asian Test Symposium, 2007

Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Power-Constrained SOC Test Schedules through Utilization of Functional Buses.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006


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