Igor Aleksejev

Orcid: 0000-0001-5931-0167

According to our database1, Igor Aleksejev authored at least 11 papers between 2008 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
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PhD thesis 
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Links

Online presence:

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Bibliography

2017
Run-time reconfigurable instruments for advanced board-level testing.
IEEE Instrum. Meas. Mag., 2017

2016
Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures.
J. Electron. Test., 2016

On coverage of timing related faults at board level.
Proceedings of the 21th IEEE European Test Symposium, 2016

2015
Complex delay fault reasoning with sequential 7-valued algebra.
Proceedings of the 16th Latin-American Test Symposium, 2015

Virtual reconfigurable scan-chains on FPGAs for optimized board test.
Proceedings of the 16th Latin-American Test Symposium, 2015

2012
FPGA-based synthetic instrumentation for board test.
Proceedings of the 2012 IEEE International Test Conference, 2012

Embedded synthetic instruments for Board-Level testing.
Proceedings of the 17th IEEE European Test Symposium, 2012

2011
Invited paper: System-wide fault management based on IEEE P1687 IJTAG.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

2009
Turning JTAG inside out for fast extended test access.
Proceedings of the 10th Latin American Test Workshop, 2009

Fast extended test access via JTAG and FPGAs.
Proceedings of the 2009 IEEE International Test Conference, 2009

2008
Reseeding using compaction of pre-generated LFSR sub-sequences.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008


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