Jaan Raik
Orcid: 0000-0001-8113-020XAffiliations:
- Tallinn University of Technology, Department of Computer Systems, Estonia
According to our database1,
Jaan Raik
authored at least 203 papers
between 1997 and 2024.
Collaborative distances:
Collaborative distances:
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on ati.ttu.ee
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Bibliography
2024
A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks.
ACM Comput. Surv., June, 2024
ACM Comput. Surv., February, 2024
SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators.
CoRR, 2024
CoRR, 2024
Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators.
CoRR, 2024
Springer, ISBN: 978-3-031-44733-4, 2024
2023
IEEE Trans. Very Large Scale Integr. Syst., June, 2023
Microprocess. Microsystems, March, 2023
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
Fully-Fusible Convolutional Neural Networks for End-to-End Fused Architecture with FPGA Implementation.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
Adaptive Kalman Filter Based Data Aggregation in Fault-Resilient Underwater Sensor Networks.
Proceedings of the 24th International Conference on Digital Signal Processing, 2023
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
IEEE Access, 2022
An Efficient Analog Convolutional Neural Network Hardware Accelerator Enabled by a Novel Memoryless Architecture for Insect-Sized Robots.
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022
High-Level Fault Diagnosis in RISC Processors with Implementation-Independent Functional Test.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
2021
Sensors, 2021
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2021, Oslo, 2021
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 30th IEEE Asian Test Symposium, 2021
2020
Calculation of probabilistic testability measures for digital circuits with Structurally Synthesized BDDs.
Microprocess. Microsystems, 2020
High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors.
J. Electron. Test., 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020
Proceedings of the IEEE European Test Symposium, 2020
Proceedings of the 16th European Dependable Computing Conference, 2020
SCAAT: Secure Cache Alternative Address Table for mitigating cache logical side-channel attacks.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
Adjustable self-healing methodology for accelerated functions in heterogeneous systems.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
Implementation-Independent Functional Test for Transition Delay Faults in Microprocessors.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Microprocess. Microsystems, 2019
High-Level Combined Deterministic and Pseudoexhuastive Test Generation for RISC Processors.
CoRR, 2019
Proceedings of the VLSI-SoC: New Technology Enabler, 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019
Proceedings of the IEEE Latin American Test Symposium, 2019
Proceedings of the IEEE Latin American Test Symposium, 2019
Proceedings of the IEEE International Test Conference, 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the 2019 Forum for Specification and Design Languages, 2019
An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements.
Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019
High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors.
Proceedings of the 24th IEEE European Test Symposium, 2019
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019
2018
Microelectron. Reliab., 2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Upgrading QoSinNoC: Efficient Routing for Mixed-Criticality Applications and Power Analysis.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
AWAIT: An Ultra-Lightweight Soft-Error Mitigation Mechanism for Network-on-Chip Links.
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018
Proceedings of the 25th International Conference "Mixed Design of Integrated Circuits and System", 2018
Proceedings of the 7th Mediterranean Conference on Embedded Computing, 2018
Proceedings of the IEEE International Test Conference in Asia, 2018
Proceedings of the IEEE International Test Conference in Asia, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018
QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
2017
Microprocess. Microsystems, 2017
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017
Comprehensive performance and robustness analysis of 2D turn models for network-on-chips.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 13th International Conference on ICT in Education, 2017
Proceedings of the 22nd IEEE European Test Symposium, 2017
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017
From online fault detection to fault management in Network-on-Chips: A ground-up approach.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Resting EEG functional connectivity and graph theoretical measures for discrimination of depression.
Proceedings of the 2017 IEEE EMBS International Conference on Biomedical & Health Informatics, 2017
2016
J. Electron. Test., 2016
CoRR, 2016
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
SoCDep<sup>2</sup>: A framework for dependable task deployment on many-core systems under mixed-criticality constraints.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016
Proceedings of the 17th Latin-American Test Symposium, 2016
Designing reliable cyber-physical systems overview associated to the special session at FDL'16.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs.
Proceedings of the 25th IEEE Asian Test Symposium, 2016
2015
Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra.
Microprocess. Microsystems, 2015
Microprocess. Microsystems, 2015
Fault Collapsing in Digital Circuits Using Fast Fault Dominance and Equivalence Analysis with SSBDDs.
Proceedings of the VLSI-SoC: Design for Reliability, Security, and Low Power, 2015
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015
Shared Structurally Synthesized BDDs for speeding-up parallel pattern simulation in digital circuits.
Proceedings of the Nordic Circuits and Systems Conference, 2015
A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015
Proceedings of the 16th Latin-American Test Symposium, 2015
Immortalizing many-core systems early experiences of the horizon 2020 action IMMORTAL.
Proceedings of the 2015 International Conference on High Performance Computing & Simulation, 2015
Proceedings of the 2015 International Conference on Advances in Computing, 2015
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015
SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015
New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015
2014
Proceedings of the 15th Latin American Test Workshop, 2014
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014
Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation.
Proceedings of the Applications of Evolutionary Computation - 17th European Conference, 2014
Proceedings of the 19th IEEE European Test Symposium, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
2013
Automated design error debug using high-level decision diagrams and mutation operators.
Microprocess. Microsystems, 2013
Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013
Proceedings of the 14th Latin American Test Workshop, 2013
Proceedings of the International Conference on Advances in Computing, 2013
Proceedings of the East-West Design & Test Symposium, 2013
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013
2012
J. Electron. Test., 2012
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Proceedings of the 13th International Workshop on Microprocessor Test and Verification, 2012
Proceedings of the 13th Latin American Test Workshop, 2012
Proceedings of the 13th Latin American Test Workshop, 2012
Diagnosis and correction of multiple design errors using critical path tracing and mutation analysis.
Proceedings of the 13th Latin American Test Workshop, 2012
Proceedings of the 2012 International Symposium on System on Chip, 2012
Automated correction of design errors by edge redirection on High-Level Decision Diagrams.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the Hardware and Software: Verification and Testing, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
FP7 collaborative research project DIAMOND: Diagnosis, error modeling and correction for reliable systems design.
Proceedings of the 17th IEEE European Test Symposium, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012
2011
Proceedings of the 12th Latin American Test Workshop, 2011
Interactive presentation abstract: Automated correction of design errors by edge redirection on high-level decision diagrams.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011
Proceedings of the 9th East-West Design & Test Symposium, 2011
Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits.
Proceedings of the 16th European Test Symposium, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
2010
Proceedings of the 11th Latin American Test Workshop, 2010
Structural fault collapsing by superposition of BDDs for test generation in digital circuits.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 2010 East-West Design & Test Symposium, 2010
Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips.
IET Comput. Digit. Tech., 2009
J. Electron. Test., 2009
Diagnozer: A laboratory tool for teaching research in diagnosis of electronic systems.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2009
Proceedings of the 10th Latin American Test Workshop, 2009
Proceedings of the 10th Latin American Test Workshop, 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
2008
Microprocess. Microsystems, 2008
J. Syst. Archit., 2008
Distributed Approach for Genetic Test Generation in the Field of Digital Electronics.
Proceedings of the Intelligent Distributed Computing, Systems and Applications, Proceedings of the 2nd International Symposium on Intelligent Distributed Computing, 2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Proceedings of the 13th European Test Symposium, 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008
Proceedings of the 17th IEEE Asian Test Symposium, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
IET Comput. Digit. Tech., 2007
Proceedings of the 12th European Test Symposium, 2007
Proceedings of the 12th European Test Symposium, 2007
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
2006
Fault Simulation with Parallel Critical Path Tracing for Combinatorial Circuits Using Structurally Synthesized BDDs.
Proceedings of the 7th Latin American Test Workshop, 2006
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006
Proceedings of the 15th Asian Test Symposium, 2006
2005
J. Electron. Test., 2005
Proceedings of the 10th European Test Symposium, 2005
Proceedings of the Dependable Computing, 2005
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005
An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005
2004
Proceedings of the Virtual Enterprises and Collaborative Networks, IFIP 18th World Computer Congress, TC5 / WG5.5, 2004
Proceedings of the Field Programmable Logic and Application, 2004
2003
Proceedings of the 2003 International Symposium on System-on-Chip, 2003
2002
Microelectron. Reliab., 2002
Fast static compaction of tests composed of independent sequences: basic properties and comparison of methods.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002
Proceedings of the 2002 Design, 2002
2001
Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement.
Microelectron. Reliab., 2001
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
2000
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations.
J. Electron. Test., 2000
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000
Back-tracing and event-driven techniques in high-level simulation with decision diagrams.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the 5th European Test Workshop, 2000
Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams.
Proceedings of the 2000 Design, 2000
1999
Proceedings of the 4th European Test Workshop, 1999
Proceedings of the 1999 Design, 1999
1997
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997