Jaan Raik

According to our database1, Jaan Raik authored at least 131 papers between 1997 and 2019.

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Bibliography

2019
Mixed-level identification of fault redundancy in microprocessors.
Proceedings of the IEEE Latin American Test Symposium, 2019

Software-Based Mitigation for Memory Address Decoder Aging.
Proceedings of the IEEE Latin American Test Symposium, 2019

Fault-Aware Performance Assessment Approach for Embedded Networks.
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

New categories of Safe Faults in a processor-based Embedded System.
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

2018
Fast identification of true critical paths in sequential circuits.
Microelectronics Reliability, 2018

Design Understanding: From Logic to Specification*.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Upgrading QoSinNoC: Efficient Routing for Mixed-Criticality Applications and Power Analysis.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

AWAIT: An Ultra-Lightweight Soft-Error Mitigation Mechanism for Network-on-Chip Links.
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018

Hierarchical Timing-Critical Paths Analysis in Sequential Circuits.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Towards Multidimensional Verification: Where Functional Meets Non-Functional.
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

Parallel Critical Path Tracing Fault Simulation in Sequential Circuits.
Proceedings of the 25th International Conference "Mixed Design of Integrated Circuits and System", 2018

Reliability Improvements for Multiprocessor Systems by Health-Aware Task Scheduling.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Software-Level TMR Approach for On-Board Data Processing in Space Applications.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

From RTL Liveness Assertions to Cost-Effective Hardware Checkers.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017
Modeling and simulation of circuits with shared structurally synthesized BDDs.
Microprocessors and Microsystems - Embedded Hardware Design, 2017

Fault-resilient NoC router with transparent resource allocation.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017

High-level test generation for processing elements in many-core systems.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017

Comprehensive performance and robustness analysis of 2D turn models for network-on-chips.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Multi-Fragment Markov Model Guided Online Test Generation for MPSoC.
Proceedings of the 13th International Conference on ICT in Education, 2017

Automated area and coverage optimization of minimal latency checkers.
Proceedings of the 22nd IEEE European Test Symposium, 2017

A scalable technique to identify true critical paths in sequential circuits.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

From online fault detection to fault management in Network-on-Chips: A ground-up approach.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

BASTION: Board and SoC test instrumentation for ageing and no failure found.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits.
J. Electronic Testing, 2016

Foreword.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

SoCDep2: A framework for dependable task deployment on many-core systems under mixed-criticality constraints.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

A novel random approach to diagnostic test generation.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

Logic-based implementation of fault-tolerant routing in 3D network-on-chips.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

Gate-level modelling of NBTI-induced delays under process variations.
Proceedings of the 17th Latin-American Test Symposium, 2016

Designing reliable cyber-physical systems overview associated to the special session at FDL'16.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016

A synthesis-agnostic behavioral fault model for high gate-level fault coverage.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

Functional self-test of high-performance pipe-lined signal processing architectures.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

Fault Collapsing in Digital Circuits Using Fast Fault Dominance and Equivalence Analysis with SSBDDs.
Proceedings of the VLSI-SoC: Design for Reliability, Security, and Low Power, 2015

Scalable algorithm for structural fault collapsing in digital circuits.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Automated minimization of concurrent online checkers for Network-on-Chips.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

Shared Structurally Synthesized BDDs for speeding-up parallel pattern simulation in digital circuits.
Proceedings of the Nordic Circuits and Systems Conference, 2015

A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG.
Proceedings of the 16th Latin-American Test Symposium, 2015

Immortalizing many-core systems early experiences of the horizon 2020 action IMMORTAL.
Proceedings of the 2015 International Conference on High Performance Computing & Simulation, 2015

FSMD RTL design manipulation for clock interface abstraction.
Proceedings of the 2015 International Conference on Advances in Computing, 2015

A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014
Automated Design Error Localization in RTL Designs.
IEEE Design & Test, 2014

Hierarchical identification of NBTI-critical gates in nanoscale logic.
Proceedings of the 15th Latin American Test Workshop, 2014

Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation.
Proceedings of the Applications of Evolutionary Computation - 17th European Conference, 2014

Logic simulation and fault collapsing with shared structurally synthesized bdds.
Proceedings of the 19th IEEE European Test Symposium, 2014

Critical Path Tracing Based Simulation of Transition Delay Faults.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013
Automated design error debug using high-level decision diagrams and mutation operators.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

At-speed self-testing of high-performance pipe-lined processing architectures.
Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013

Assessment of diagnostic test for automated bug localization.
Proceedings of the 14th Latin American Test Workshop, 2013

Performance analysis of cosimulating processor core in VHDL and SystemC.
Proceedings of the International Conference on Advances in Computing, 2013

Comparison of Model-Based Error Localization algorithms for C designs.
Proceedings of the East-West Design & Test Symposium, 2013

Synthesis of multiple fault oriented test groups from single fault test sets.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

Identifying NBTI-Critical Paths in Nanoscale Logic.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Extensible open-source framework for translating RTL VHDL IP cores to SystemC.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012
Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints.
J. Electronic Testing, 2012

On the Reuse of TLM Mutation Analysis at RTL.
J. Electronic Testing, 2012

A scalable model based RTL framework zamiaCAD for static analysis.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Localization of Bugs in Processor Designs Using zamiaCAD Framework.
Proceedings of the 13th International Workshop on Microprocessor Test and Verification, 2012

About robustness of test patterns regarding multiple faults.
Proceedings of the 13th Latin American Test Workshop, 2012

PSL assertion checkers synthesis with ASM based HLS tool ABELITE.
Proceedings of the 13th Latin American Test Workshop, 2012

Diagnosis and correction of multiple design errors using critical path tracing and mutation analysis.
Proceedings of the 13th Latin American Test Workshop, 2012

Ultra-low latency NoC testing via pseudo-random test pattern compaction.
Proceedings of the 2012 International Symposium on System on Chip, 2012

Automated correction of design errors by edge redirection on High-Level Decision Diagrams.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

FoREnSiC- An Automatic Debugging Environment for C Programs.
Proceedings of the Hardware and Software: Verification and Testing, 2012

Combining dynamic slicing and mutation operators for ESL correction.
Proceedings of the 17th IEEE European Test Symposium, 2012

FP7 collaborative research project DIAMOND: Diagnosis, error modeling and correction for reliable systems design.
Proceedings of the 17th IEEE European Test Symposium, 2012

How to Prove that a Circuit is Fault-Free?
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Multiple stuck-at-fault detection theorem.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Low-area boundary BIST architecture for mesh-like network-on-chip.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
Interactive presentation abstract: Automated correction of design errors by edge redirection on high-level decision diagrams.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

Automated test bench generation for high-level synthesis flow ABELITE.
Proceedings of the 9th East-West Design & Test Symposium, 2011

Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits.
Proceedings of the 16th European Test Symposium, 2011

Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Defect-oriented module-level fault diagnosis in digital circuits.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Probabilistic equivalence checking based on high-level decision diagrams.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010
Structural fault collapsing by superposition of BDDs for test generation in digital circuits.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Fault collapsing with linear complexity in digital circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

An approach for PSL assertion coverage analysis with high-level decision diagrams.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits.
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

Constraint-based test pattern generation at the Register-Transfer Level.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Parallel X-fault simulation with critical path tracing technique.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips.
IET Computers & Digital Techniques, 2009

PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams.
J. Electronic Testing, 2009

Diagnozer: A laboratory tool for teaching research in diagnosis of electronic systems.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2009

Structurally synthesized multiple input BDDs for simulation of digital circuits.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008
Embedded fault diagnosis in digital systems with BIST.
Microprocessors and Microsystems - Embedded Hardware Design, 2008

Mixed hierarchical-functional fault models for targeting sequential cores.
Journal of Systems Architecture - Embedded Systems Design, 2008

Distributed Approach for Genetic Test Generation in the Field of Digital Electronics.
Proceedings of the Intelligent Distributed Computing, Systems and Applications, Proceedings of the 2nd International Symposium on Intelligent Distributed Computing, 2008

Reseeding using compaction of pre-generated LFSR sub-sequences.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation.
Proceedings of the 13th European Test Symposium, 2008

Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Code Coverage Analysis using High-Level Decision Diagrams.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Web-Based Framework for Parallel Distributed Test.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Untestable Fault Identification in Sequential Circuits Using Model-Checking.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

Parallel fault backtracing for calculation of fault coverage.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
FPGA-based fault emulation of synchronous sequential circuits.
IET Computers & Digital Techniques, 2007

Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs.
Proceedings of the 12th European Test Symposium, 2007

Test Configurations for Diagnosing Faulty Links in NoC Switches.
Proceedings of the 12th European Test Symposium, 2007

Fault Diagnosis in Integrated Circuits with BIST.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Hierarchical Identification of Untestable Faults in Sequential Circuits.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Layout to Logic Defect Analysis for Hierarchical Test Generation.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006
High-Level Decision Diagram based Fault Models for Targeting FSMs.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2005
A New Testability Calculation Method to Guide RTL Test Generation.
J. Electronic Testing, 2005

DOT: new deterministic defect-oriented ATPG tool.
Proceedings of the 10th European Test Symposium, ETS 2005, Tallinn, 2005

Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs.
Proceedings of the Dependable Computing, 2005

Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Improved Fault Emulation for Synchronous Sequential Circuits.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004
Web-Based Environment for Digital Electronics Test Tools.
Proceedings of the Virtual Enterprises and Collaborative Networks, IFIP 18th World Computer Congress, TC5 / WG5.5, 2004

Evaluating Fault Emulation on FPGA.
Proceedings of the Field Programmable Logic and Application, 2004

2002
Hierarchical test generation for combinational circuits with real defects coverage.
Microelectronics Reliability, 2002

Multi-Level Fault Simulation of Digital Systems on Decision Diagrams.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Internet-Based Collaborative Test Generation with MOSCITO.
Proceedings of the 2002 Design, 2002

2001
Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement.
Microelectronics Reliability, 2001

Defect-Oriented Fault Simulation and Test Generation in Digital Circuits.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

2000
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations.
J. Electronic Testing, 2000

Efficient Hierarchical Approach to Test Generation for Digital Systems.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Back-tracing and event-driven techniques in high-level simulation with decision diagrams.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams.
Proceedings of the 2000 Design, 2000

1999
Cycle-based Simulation with Decision Diagrams.
Proceedings of the 1999 Design, 1999

Sequential Circuit Test Generation Using Decision Diagram Models.
Proceedings of the 1999 Design, 1999

1997
Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997


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