In Man Kang
Orcid: 0000-0002-7726-9740
According to our database1,
In Man Kang
authored at least 17 papers
between 2004 and 2022.
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Bibliography
2022
Systematic Engineering of Metal Ion Injection in Memristors for Complex Neuromorphic Computing with High Energy Efficiency.
Adv. Intell. Syst., 2022
2021
IEEE Access, 2021
Polycrystalline-Silicon-MOSFET-Based Capacitorless DRAM With Grain Boundaries and Its Performances.
IEEE Access, 2021
2020
Enhancement Mode Flexible SnO<sub>2</sub> Thin Film Transistors Via a UV/Ozone-Assisted Sol-Gel Approach.
IEEE Access, 2020
Fabrication of AlGaN/GaN Fin-Type HEMT Using a Novel T-Gate Process for Improved Radio-Frequency Performance.
IEEE Access, 2020
2019
Employing Genetic Algorithm as an Efficient Alternative to Parameter Sweep Based Multi-Layer Thickness Optimization in Solar Cells.
CoRR, 2019
2016
InGaAs-based junctionless transistor with dual-spacer dielectric for low power loss and high frequency mobile network system.
Proceedings of the 2016 International Conference on Information Networking, 2016
Design optimization of Si/Ge-based heterojunction arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET) which applicable for future mobile communication systems.
Proceedings of the 2016 International Conference on Information Networking, 2016
Proceedings of the 46th European Solid-State Device Research Conference, 2016
2015
RF performance of InGaAs-based T-gate junctionless field-effect transistors which applicable for high frequency network systems.
Proceedings of the 2015 International Conference on Information Networking, 2015
Fabrication of high performance AlGaN/GaN FinFET by utilizing anisotropic wet etching in TMAH solution.
Proceedings of the 45th European Solid State Device Research Conference, 2015
2014
IEICE Trans. Electron., 2014
2013
Rigorous Design and Analysis of Tunneling Field-Effect Transistor with Hetero-Gate-Dielectric and Tunneling-Boost n-Layer.
IEICE Trans. Electron., 2013
2012
Performance of Gate-All-Around Tunneling Field-Effect Transistors Based on Si<sub>1-<i>x</i></sub> Ge<sub><i>x</i></sub> Layer.
IEICE Trans. Electron., 2012
Simulation study on scaling limit of silicon tunneling field-effect transistor under tunneling-predominance.
IEICE Electron. Express, 2012
2010
Investigation of source-to-drain capacitance by DIBL effect of silicon nanowire MOSFETs.
IEICE Electron. Express, 2010
2004
Effects of electrical stress on mid-gap interface trap density and capture cross sections in n-MOSFETs characterized by pulsed interface probing measurements.
Microelectron. Reliab., 2004