Ioannis Kouretas

Orcid: 0000-0002-8574-8469

According to our database1, Ioannis Kouretas authored at least 37 papers between 2002 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A Multiplier-Free RNS-Based CNN Accelerator Exploiting Bit-Level Sparsity.
IEEE Trans. Emerg. Top. Comput., 2024

An end-to-end RNS CNN Accelerator.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023
On the modulo 2<i><sup>n</sup></i>+1 addition and subtraction for weighted operands.
Microprocess. Microsystems, 2023

A Regularization Approach to Maximize Common Sub-Expressions in Neural Network Weights.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

Improving Residue-Level Sparsity in RNS-based Neural Network Hardware Accelerators via Regularization.
Proceedings of the 30th IEEE Symposium on Computer Arithmetic, 2023

Modified Logarithmic Multiplication Approximation for Machine Learning.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
Fetus Heart Rate Monitoring: A Preliminary Research Study With Remote Sensing.
IEEE Consumer Electron. Mag., 2022

A High-performance RNS LSTM block.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Hardware Aspects of Parallel Neural Network Implementation.
Proceedings of the 10th International Conference on Modern Circuits and Systems Technologies, 2021

Simplified Hardware Implementation of Memoryless Dot Product for Neural Network Inference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

On Reducing the Number of Multiplications in RNS-based CNN Accelerators.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

2020
Implementing the Residue Logarithmic Number System Using Interpolation and Cotransformation.
IEEE Trans. Computers, 2020

2019
Radix-3 low-complexity modulo-M multipliers.
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

One-Hot Residue Logarithmic Number Systems.
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

Simplified Hardware Implementation of the Softmax Activation Function.
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

Under- and Overflow Detection in the Residue Logarithmic Number System.
Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019

2018
Effective Capacity of Fluctuating Two-Ray Channels with Arbitrary Fading Parameters.
Proceedings of the 19th IEEE International Workshop on Signal Processing Advances in Wireless Communications, 2018

Logarithmic number system for deep learning.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

Hardware aspects of Long Short Term Memory.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Simplified Deep-Learning-based decoders for linear block codes.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2016
Dynamic delay variation behaviour of RNS multiply-add architectures.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2013
Low-Power Logarithmic Number System Addition/Subtraction and Their Impact on Digital Filters.
IEEE Trans. Computers, 2013

Delay-variation-tolerant FIR filter architectures based on the Residue Number System.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Residue arithmetic for designing multiply-add units in the presence of non-gaussian variation.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A Residue Logarithmic Number System ALU using interpolation and cotransformation.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

Towards a Quaternion Complex Logarithmic Number System.
Proceedings of the 20th IEEE Symposium on Computer Arithmetic, 2011

2010
Residue Arithmetic for Designing Low-Power Multiply-Add Units.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

Residue arithmetic bases for reducing delay variation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

RNS multi-voltage low-power multiply-add unit.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
A Low-Complexity High-Radix RNS Multiplier.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Residue Arithmetic for Variation-Tolerant Design of Multiply-Add Units.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

High-radix residue arithmetic bases for low-power DSP systems.
Proceedings of the 16th International Conference on Digital Signal Processing, 2009

Variation-tolerant Design Using Residue Number System.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008
Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

2007
Low-Power Digital Filtering Based on the Logarithmic Number System.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

2003
High-radix redundant circuits for RNS modulo r<sup>n</sup>-1, r<sup>n</sup>, or r<sup>n</sup>+1.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
High-radix modulo r<sup>n</sup> - 1 multipliers and adders.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002


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