Ioannis Kouretas

According to our database, Ioannis Kouretas authored at least 36 papers between 2002 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

On the modulo 2<i>ⁿ</i>+1 addition and subtraction for weighted operands.

Constantinos Efstathiou, Ioannis Kouretas, Paris Kitsos

Microprocess. Microsystems, 2023

A Regularization Approach to Maximize Common Sub-Expressions in Neural Network Weights.

Emmanouil Kavvousanos, Ioannis Kouretas, Vassilis Paliouras, Thanos Stouraitis

Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

A multiplier-Free RNS-Based CNN accelerator exploiting bit-Level sparsity.

Vasilis Sakellariou, Vassilis Paliouras, Ioannis Kouretas, Hani H. Saleh, Thanos Stouraitis

Proceedings of the 30th IEEE Symposium on Computer Arithmetic, 2023

Improving Residue-Level Sparsity in RNS-based Neural Network Hardware Accelerators via Regularization.

Emmanouil Kavvousanos, Vasilis Sakellariou, Ioannis Kouretas, Vassilis Paliouras, Thanos Stouraitis

Proceedings of the 30th IEEE Symposium on Computer Arithmetic, 2023

Modified Logarithmic Multiplication Approximation for Machine Learning.

Ioannis Kouretas, Vassilis Paliouras, Thanos Stouraitis

Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022

Fetus Heart Rate Monitoring: A Preliminary Research Study With Remote Sensing.

Anastasios G. Skrivanos, Evangelia I. Kosma, Spyridon K. Chronopoulos, Ioannis Kouretas, Dimitrios Dimopoulos, Georgios Petrakos, Elena Alhazidou, Vasilis Christofilakis, Nafsika Ziavra, Kostas P. Peppas, Eugenia I. Toki

IEEE Consumer Electron. Mag., 2022

A High-performance RNS LSTM block.

Vasilis Sakellariou, Vassilis Paliouras, Ioannis Kouretas, Hani H. Saleh, Thanos Stouraitis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

Hardware Aspects of Parallel Neural Network Implementation.

Ioannis Kouretas, Vassilis Paliouras

Proceedings of the 10th International Conference on Modern Circuits and Systems Technologies, 2021

Simplified Hardware Implementation of Memoryless Dot Product for Neural Network Inference.

Ioannis Kouretas, Vassilis Paliouras

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

On Reducing the Number of Multiplications in RNS-based CNN Accelerators.

Vasilis Sakellariou, Vassilis Paliouras, Ioannis Kouretas, Hani H. Saleh, Thanos Stouraitis

Proceedings of the 28th IEEE International Conference on Electronics, 2021

2020

Implementing the Residue Logarithmic Number System Using Interpolation and Cotransformation.

Mark G. Arnold, Vassilis Paliouras, Ioannis Kouretas

IEEE Trans. Computers, 2020

2019

Radix-3 low-complexity modulo-M multipliers.

Ioannis Kouretas, Vassilis Paliouras

Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

One-Hot Residue Logarithmic Number Systems.

Mark G. Arnold, Ioannis Kouretas, Vassilis Paliouras, Austin Morgan

Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

Simplified Hardware Implementation of the Softmax Activation Function.

Ioannis Kouretas, Vassilis Paliouras

Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

Under- and Overflow Detection in the Residue Logarithmic Number System.

Mark G. Arnold, Ioannis Kouretas, Vassilis Paliouras, John R. Cowles

Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019

2018

Effective Capacity of Fluctuating Two-Ray Channels with Arbitrary Fading Parameters.

Kostas P. Peppas, Ioannis Kouretas, Jiayi Zhang, Spyridon K. Chronopoulos

Proceedings of the 19th IEEE International Workshop on Signal Processing Advances in Wireless Communications, 2018

Logarithmic number system for deep learning.

Ioannis Kouretas, Vassilis Paliouras

Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

Hardware aspects of Long Short Term Memory.

Ioannis Kouretas, Vassilis Paliouras

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Simplified Deep-Learning-based decoders for linear block codes.

Emmanouil Kavvousanos, Vassilis Paliouras, Ioannis Kouretas

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2016

Dynamic delay variation behaviour of RNS multiply-add architectures.

Kleanthis Papachatzopoulos, Ioannis Kouretas, Vassilis Paliouras

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2013

Low-Power Logarithmic Number System Addition/Subtraction and Their Impact on Digital Filters.

Ioannis Kouretas, Charalambos Basetas, Vassilis Paliouras

IEEE Trans. Computers, 2013

Delay-variation-tolerant FIR filter architectures based on the Residue Number System.

Ioannis Kouretas, Vassilis Paliouras

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

Residue arithmetic for designing multiply-add units in the presence of non-gaussian variation.

Ioannis Kouretas, Vassilis Paliouras

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

A Residue Logarithmic Number System ALU using interpolation and cotransformation.

Mark G. Arnold, Ioannis Kouretas, Vassilis Paliouras

Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

Towards a Quaternion Complex Logarithmic Number System.

Mark G. Arnold, John R. Cowles, Vassilis Paliouras, Ioannis Kouretas

Proceedings of the 20th IEEE Symposium on Computer Arithmetic, 2011

2010

Residue Arithmetic for Designing Low-Power Multiply-Add Units.

Ioannis Kouretas, Vassilis Paliouras

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

Residue arithmetic bases for reducing delay variation.

Ioannis Kouretas, Vassilis Paliouras

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

RNS multi-voltage low-power multiply-add unit.

Ioannis Kouretas, Vassilis Paliouras

Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009

A Low-Complexity High-Radix RNS Multiplier.

Ioannis Kouretas, Vassilis Paliouras

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Residue Arithmetic for Variation-Tolerant Design of Multiply-Add Units.

Ioannis Kouretas, Vassilis Paliouras

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

High-radix residue arithmetic bases for low-power DSP systems.

Ioannis Kouretas, Vassilis Paliouras

Proceedings of the 16th International Conference on Digital Signal Processing, 2009

Variation-tolerant Design Using Residue Number System.

Ioannis Kouretas, Vassilis Paliouras

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008

Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication.

Ioannis Kouretas, Vassilis Paliouras

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

2007

Low-Power Digital Filtering Based on the Logarithmic Number System.

Charalambos Basetas, Ioannis Kouretas, Vassilis Paliouras

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

2003

High-radix redundant circuits for RNS modulo rⁿ-1, rⁿ, or rⁿ+1.

Ioannis Kouretas, Vassilis Paliouras

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

High-radix modulo rⁿ - 1 multipliers and adders.

Ioannis Kouretas, Vassilis Paliouras

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002