Costas Efstathiou

According to our database, Costas Efstathiou authored at least 86 papers between 1984 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

On the modulo 2<i>ⁿ</i>+1 addition and subtraction for weighted operands.

Constantinos Efstathiou, Ioannis Kouretas, Paris Kitsos

Microprocess. Microsystems, 2023

2022

Efficient Dynamic Logic Magnitude Comparators.

Constantinos Efstathiou, Laura Agalioti, Yiorgos Tsiatouhas

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

2021

Efficient majority logic magnitude comparator design.

Constantinos Efstathiou, Paris Kitsos

Microprocess. Microsystems, 2021

2020

On the Diminished-1 Modulo 2n+1 Addition and Subtraction.

Constantinos Efstathiou, Kiamal Z. Pekmestzi, Nikolaos Moschopoulos

J. Circuits Syst. Comput., 2020

Efficient design of magnitude and 2's complement comparators.

Fotios Ntouskas, Constantinos Efstathiou, Kiamal Z. Pekmestzi

Integr., 2020

2019

On the Static CMOS Implementation of Magnitude Comparators.

Costas Efstathiou, Yiorgos Tsiatouhas

Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

2018

Low Power and High Speed Static CMOS Digital Magnitude Comparators.

Costas Efstathiou, K. Dimolikas, Christoforos Papaioannou, Yiorgos Tsiatouhas

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Programmable logic for single-output functions.

Ioannis Voyiatzis, Constantinos Efstathiou, Cleo Sgouropoulou

Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

SIC pair generation in near-optimal time with carry-look ahead adders.

Ioannis Voyiatzis, Costas Efstathiou

Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

2017

On the generation of binary functions with low-overhead.

Ioannis Voyiatzis, Costas Efstathiou

Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

2016

Software-based SIC pair Generation.

Ioannis Voyiatzis, Costas Efstathiou, Kiriakos Patriarcheas

Proceedings of the 20th Pan-Hellenic Conference on Informatics, 2016

Low Cost Boolean Function generation.

Ioannis Voyiatzis, Costas Efstathiou

Proceedings of the 20th Pan-Hellenic Conference on Informatics, 2016

Fused modulo 2n + 1 add-multiply unit for weighted operands.

Kiamal Z. Pekmestzi, Kostas Tsoumanis, Constantinos Efstathiou

Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

Design of Efficient 1's Complement Modified Booth Multiplier.

Kiamal Z. Pekmestzi, Constantinos Efstathiou

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015

Accumulator-based generation for serial TPG.

Ioannis Voyiatzis, Costas Efstathiou

Proceedings of the 19th Panhellenic Conference on Informatics, 2015

On the use of hard faults to generate test sets.

Ioannis Voyiatzis, Costas Efstathiou

Proceedings of the 19th Panhellenic Conference on Informatics, 2015

Modulo 2n ± 1 Fused Add-Multiply Units.

Constantinos Efstathiou, Kostas Tsoumanis, Kiamal Z. Pekmestzi, Ioannis Voyiatzis

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Detecting untestable hardware Trojan with non-intrusive concurrent on line testing.

Ioannis Voyiatzis, Cleo Sgouropoulou, Constantinos Efstathiou

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

A concurrent BIST scheme for read only memories.

Ioannis Voyiatzis, Cleo Sgouropoulou, Costas Efstathiou

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Test set embedding into hardware generated sequences using an embedding algorithm.

Ioannis Voyiatzis, Dimitris J. Kavvadias, S. Sinitos, K. Vlahantonis, P. Kyrkos, Cleo Sgouropoulou, Costas Efstathiou

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

2014

Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells.

Ioannis Voyiatzis, Costas Efstathiou

IEEE Trans. Very Large Scale Integr. Syst., 2014

An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator.

Kostas Tsoumanis, Sotirios Xydis, Constantinos Efstathiou, Nikolaos Moschopoulos, Kiamal Z. Pekmestzi

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Efficient modulo 2ⁿ+1 multiply and multiply-add units based on modified Booth encoding.

Constantinos Efstathiou, Nikos K. Moshopoulos, Nicholas Axelos, Kiamal Z. Pekmestzi

Integr., 2014

Stealth Assessment of Hardware Trojans in simple Processors.

I. Nikopoulos, Athanasios Milidonis, Costas Efstathiou, Cleo Sgouropoulou, Ioannis Voyiatzis

Proceedings of the 18th Panhellenic Conference on Informatics, 2014

Modulo 2ⁿ+1 addition and multiplication for redundant operands.

Kostas Tsoumanis, Constantinos Efstathiou, Kiamal Z. Pekmestzi

Proceedings of the 9th International Design and Test Symposium, 2014

High performance MAC designs.

Nikolaos Eftaxiopoulos-Sarris, Georgios Zervakis, Kiamal Z. Pekmestzi, Costas Efstathiou

Proceedings of the 9th International Design and Test Symposium, 2014

Fused modulo 2ⁿ - 1 add-multiply unit.

Kostas Tsoumanis, Kiamal Z. Pekmestzi, Constantinos Efstathiou

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Low overhead output response compaction in RAS architectures.

Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Accumulator-based self-adjusting output data compression for embedded word-organized DRAMs.

Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

On the design of efficient modulo 2ⁿ+1 multiply-add-add units.

Constantinos Efstathiou, Kostas Tsoumanis, Kiamal Z. Pekmestzi, Ioannis Voyiatzis

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

2013

New High-Speed Multioutput Carry Look-Ahead Adders.

Costas Efstathiou, Zaher Owda, Yiorgos Tsiatouhas

IEEE Trans. Circuits Syst. II Express Briefs, 2013

An effective two-pattern test generator for Arithmetic BIST.

Ioannis Voyiatzis, Costas Efstathiou, Hera Antonopoulou, Athanasios Milidonis

Comput. Electr. Eng., 2013

On the design of modulo 2ⁿ + 1 dot product and generalized multiply-add units.

Costas Efstathiou, Nikolaos Moschopoulos, Ioannis Voyiatzis, Kiamal Z. Pekmestzi

Comput. Electr. Eng., 2013

On the design of modulo 2ⁿ±1 residue generators.

Kostas Tsoumanis, Constantinos Efstathiou, Nikolaos Moschopoulos, Kiamal Z. Pekmestzi

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

A low-cost input vector monitoring concurrent BIST scheme.

Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Test set embedding into accumulator-generated sequences targeting hard-to-detect faults.

Ioannis Voyiatzis, Stelios Neophytou, Maria K. Michael, Stavros Hadjitheophanous, Cleo Sgouropoulou, Costas Efstathiou

Proceedings of the 8th International Design and Test Symposium, 2013

Transparent testing for intra-word memory faults.

Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou

Proceedings of the 8th International Design and Test Symposium, 2013

Efficient modulo 2ⁿ+1 multiplication for the idea block cipher.

Kiamal Z. Pekmestzi, Constantinos Efstathiou, Nikolaos Moschopoulos, Kostas Tsoumanis

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Embedding test vectors in accumulator - based TPG using progressive search.

Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou

Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

Symmetric transparent online BIST for arrays of word-organized RAMs.

Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou

Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

2012

Arithmetic module-based built-in self test architecture for two-pattern testing.

Ioannis Voyiatzis, Costas Efstathiou, Hera Antonopoulou, Athanasios Milidonis

IET Comput. Digit. Tech., 2012

Test Set Embedding into Low-Power BIST Sequences Using Maximum Bipartite Matching.

Ioannis Voyiatzis, Kyriakos Axiotis, Nikolaos S. Papaspyrou, Hera Antonopoulou, Costas Efstathiou

Proceedings of the 16th Panhellenic Conference on Informatics, PCI 2012, 2012

A novel architecture to reduce test time in march-based SRAM tests.

Ioannis Voyiatzis, Costas Efstathiou, Yiorgos Tsiatouhas, Cleo Sgouropoulou

Proceedings of the 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2012

Test vector embedding in accumulators with stored carry in O(1) time.

Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou

Proceedings of the 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2012

Test set embedding into low-power sequences based on a traveling salesman problem formulation.

Ioannis Voyiatzis, Costas Efstathiou, Dimitris Magos, Cleo Sgouropoulou

Proceedings of the 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2012

ALU based address generation for RAMs.

Ioannis Voyiatzis, Costas Efstathiou, Said Hamdioui, Cleo Sgouropoulou

Proceedings of the 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2012

On the Design of Configurable Modulo 2n±1 Residue Generators.

Constantinos Efstathiou, Nikolaos Moschopoulos, Kostas Tsoumanis, Kiamal Z. Pekmestzi

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011

A Novel SRAM-Cell Based Input Vector Monitoring Concurrent BIST Architecture.

Ioannis Voyiatzis, Costas Efstathiou, Hera Antonopoulou

Proceedings of the 16th European Test Symposium, 2011

On the Design of Modulo 2^n+1 Multipliers.

Constantinos Efstathiou, Kiamal Z. Pekmestzi, Nicholas Axelos

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010

An efficient architecture for accumulator-based test generation of SIC pairs.

Ioannis Voyiatzis, Costas Efstathiou

Microelectron. J., 2010

Fast modulo 2ⁿ+1 multi-operand adders and residue generators.

Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou

Integr., 2010

On Embedding Test Sets into Hardware Generated Sequences.

Dimitris J. Kavvadias, S. Sinitos, Ioannis Voyiatzis, Hera Antonopoulou, Costas Efstathiou

Proceedings of the 14th Panhellenic Conference on Informatics, 2010

Efficient modulo 2^N+1 subtractors for weighted operands.

Costas Efstathiou

Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009

Efficient modulo 2ⁿ+1 adder architectures.

Haridimos T. Vergos, Costas Efstathiou

Integr., 2009

2008

A Unifying Approach for Weighted and Diminished-1 Modulo 2ⁿ⁺¹ Addition.

Haridimos T. Vergos, Costas Efstathiou

IEEE Trans. Circuits Syst. II Express Briefs, 2008

Efficient modulo 2ⁿ + 1 multi-operand adders.

Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007

Testable Designs of Multiple Precharged Domino Circuits.

Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou

IEEE Trans. Very Large Scale Integr. Syst., 2007

Design of efficient modulo 2ⁿ+1 multipliers.

Haridimos T. Vergos, Costas Efstathiou

IET Comput. Digit. Tech., 2007

SecurID Authenticator: On the Hardware Implementation Efficiency.

Nicolas Sklavos, Costas Efstathiou

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Implementation of HSSec: a high-speed cryptographic co-processor.

Athanasios P. Kakarountas, Haralambos Michail, Costas E. Goutis, Costas Efstathiou

Proceedings of 12th IEEE International Conference on Emerging Technologies and Factory Automation, 2007

2006

Novel Modulo 2ⁿ + 1 Multipliers.

Haridimos T. Vergos, Costas Efstathiou

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2005

Efficient Diminished-1 Modulo 2^n+1 Multipliers.

Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos

IEEE Trans. Computers, 2005

On the Design of Efficient Modular Adders.

Haridimos T. Vergos, Costas Efstathiou

J. Circuits Syst. Comput., 2005

New architectures for modulo 2N - 1 adders.

Giorgos Dimitrakopoulos, Dimitris G. Nikolos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou

Proceedings of the 12th IEEE International Conference on Electronics, 2005

2004

Fast Parallel-Prefix Modulo 2^n+1 Adders.

Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos

IEEE Trans. Computers, 2004

Modified Booth Modulo 2ⁿ-1 Multipliers.

Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos

IEEE Trans. Computers, 2004

Diminished-1 Modulo 2ⁿ + 1 Squarer Design.

Haridimos T. Vergos, Costas Efstathiou

Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

2003

Deterministic BIST for RNS Adders.

Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou

IEEE Trans. Computers, 2003

Modulo 2n±1 Adder Design Using Select-Prefix Blocks.

Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos

IEEE Trans. Computers, 2003

A Virtual Signalling Protocol for Transparently Embedding Advanced Traffic Control and Resource Management Functionality in ATM Core Networks.

K. Katzourakis, George Kormentzas, Kimon P. Kontovasilis, Costas Efstathiou

Proceedings of the Management of Multimedia Networks and Services, 2003

Efficient BIST schemes for RNS datapaths.

Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A systematic methodology for designing area-time efficient parallel-prefix modulo 2ⁿ - 1 adders.

Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

An Efficient BIST scheme for High-Speed Adders.

Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Efficient modulo 2ⁿ+1 tree multipliers for diminished-1 operands.

Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos

Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

A Family of Parallel-Pre.x Modulo 2n - 1 Adders.

Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou

Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

2002

Diminished-One Modulo 2ⁿ+1 Adder Design.

Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos

IEEE Trans. Computers, 2002

Ling adders in CMOS standard cell technologies.

Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001

A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme.

Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou

Proceedings of the 2nd Latin American Test Workshop, 2001

Concurrent Detection of Soft Errors Based on Current Monitoring.

Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Costas Efstathiou

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

On the design of modulo 2ⁿ±1 adders.

Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands.

Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou

Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001

2000

High-Speed Parallel-Prefix Modulo 2n-1 Adders.

Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos

IEEE Trans. Computers, 2000

On Testability of Multiple Precharged Domino Logic.

Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Modified Booth 1's complement and modulo 2ⁿ-1 multipliers.

Costas Efstathiou, Haridimos T. Vergos

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

1990

An Efficient TSC 1-out-of-3 Code Checker.

Antonis M. Paschalis, Costas Efstathiou, Constantine Halatsis

IEEE Trans. Computers, 1990

1984

Modular design of totally self-checking checkers for 1-out-of-n codes.

Costas Efstathiou, Constantine Halatsis

Proceedings of the Fehlertolerierende Rechensysteme, 1984