Paris Kitsos

Orcid: 0000-0003-1851-8775

Affiliations:
  • University of the Peloponnese, Electrical & Computer Engineering Department, Greece
  • Hellenic Open University, Patras, Greece


According to our database1, Paris Kitsos authored at least 89 papers between 2001 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

Online presence:

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Bibliography

2023
A Survey on RISC-V-Based Machine Learning Ecosystem.
Inf., February, 2023

On the modulo 2<i><sup>n</sup></i>+1 addition and subtraction for weighted operands.
Microprocess. Microsystems, 2023

Summary of Locating Hardware Trojans using Combinatorial Testing for Cryptographic Circuits.
Proceedings of the IEEE International Conference on Software Testing, Verification and Validation, ICST 2023, 2023

FPGA-Based Encryption System for Cloud Security.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

2022
Efficient Edge-AI Application Deployment for FPGAs.
Inf., 2022

Locating Hardware Trojans Using Combinatorial Testing for Cryptographic Circuits.
IEEE Access, 2022

FPGA-SoC Deployment of Complex Deep Neural Network for Magnitude and Phase Computations in Denoising of Speech Signal.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

2021
Efficient majority logic magnitude comparator design.
Microprocess. Microsystems, 2021

Workflow on CNN utilization and inference in FPGA for embedded applications: 6th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM 2021).
Proceedings of the 6th South-East Europe Design Automation, 2021

Importing Custom DNN Models on FPGAs.
Proceedings of the 10th Mediterranean Conference on Embedded Computing, 2021

5G Security: FPGA Implementation of SNOW-V Stream Cipher.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

2020
8-bit serialised architecture of SEED block cipher for constrained devices.
IET Circuits Devices Syst., 2020

Are ring oscillators without a combinatorial loop good enough for Hardware Trojan detection?
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2019
An efficient multi-parameter approach for FPGA hardware Trojan detection.
Microprocess. Microsystems, 2019

An 8-bit Compact Architecture of Lesamnta-LW Hash Function for Constrained Devices.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

A Very Compact Architecture of CLEFIA Block Cipher for Secure IoT Systems.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

DSD-i1: A Mixed Functionality Development Board Geared Towards Digital Systems Design Education.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

2018
Compact FPGA architectures for the two-band fast discrete Hartley transform.
Microprocess. Microsystems, 2018

A 4-bit Architecture of SEED Block Cipher for IoT Applications.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

An FPGA Hardware Trojan Detection Approach Based on Multiple Parameter Analysis.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

A Hybrid FPGA Trojan Detection Technique Based-on Combinatorial Testing and On-chip Sensing.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
On the effects of ring oscillator length and hardware Trojan size on an FPGA-based implementation of AES.
Microprocess. Microsystems, 2017

MICPRO DSD 2015 special issue.
Microprocess. Microsystems, 2017

Thermal Sensor Based Hardware Trojan Detection in FPGAs.
Proceedings of the Euromicro Conference on Digital System Design, 2017

Run-Time Effect by Inserting Hardware Trojans, in Combinational Circuits.
Proceedings of the Euromicro Conference on Digital System Design, 2017

2016
Introduction to Special Issue on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE).
Microprocess. Microsystems, 2016

An Efficient Reconfigurable Ring Oscillator for Hardware Trojan Detection.
Proceedings of the 20th Pan-Hellenic Conference on Informatics, 2016

An FPGA design for the Two-Band Fast Discrete Hartley Transform.
Proceedings of the 2016 IEEE International Symposium on Signal Processing and Information Technology, 2016

TERO-Based Detection of Hardware Trojans on FPGA Implementation of the AES Algorithm.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Efficient triggering of Trojan hardware logic.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015
Comparing design approaches for elliptic curve point multiplication over <i>GF</i>(2<sup>k</sup>) with polynomial basis representation.
Microprocess. Microsystems, 2015

A compact design of SEED block cipher.
Proceedings of the 4th Mediterranean Conference on Embedded Computing, 2015

Exciting FPGA cryptographic Trojans using combinatorial testing.
Proceedings of the 26th IEEE International Symposium on Software Reliability Engineering, 2015

A Comparison of TERO and RO Timing Sensitivity for Hardware Trojan Detection Applications.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014
Guest Editorial: Smart Grid Communications Systems.
IEEE Syst. J., 2014

Towards a hardware Trojan detection methodology.
Proceedings of the 3rd Mediterranean Conference on Embedded Computing, 2014

Cipher Text Stealing integrated in implementations of IEEE P1619 for shared storage media.
Proceedings of the 6th International Symposium on Communications, 2014

FPGA Trojan Detection Using Length-Optimized Ring Oscillators.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013
Editorial of special issue: Digital System Safety and Security.
Microprocess. Microsystems, 2013

FPGA-based performance analysis of stream ciphers ZUC, Snow3g, Grain V1, Mickey V2, Trivium and E0.
Microprocess. Microsystems, 2013

Area/performance trade-off analysis of an FPGA digit-serial <i>GF</i>(2<sup><i>m</i></sup>)GF(2m) Montgomery multiplier based on LFSR.
Comput. Electr. Eng., 2013

A high speed FPGA implementation of the 2D DCT for Ultra High Definition video coding.
Proceedings of the 18th International Conference on Digital Signal Processing, 2013

An Efficient FPGA-Based Architecture of Skein for Simple Hashing and MAC Function.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
A comparative study of hardware architectures for lightweight block ciphers.
Comput. Electr. Eng., 2012

Architectural Optimizations & Hardware Implementations of WLANs Encryption Standard.
Proceedings of the 5th International Conference on New Technologies, 2012

VLSI Design and Implementation of Homophonic Security System.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

FPGA-based Design Approaches of Keccak Hash Function.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
Bit-serial and digit-serial GF(2<sup>m</sup>)Montgomery multipliers using linear feedback shift registers.
IET Comput. Digit. Tech., 2011

Snmp for Ethernet Networks SETH: A Network Benchmark Toolkit for Managing Routers Statistical Information.
Proceedings of the 15th Panhellenic Conference on Informatics, 2011

An FPGA implementation and performance evaluation of the seed block cipher.
Proceedings of the 17th International Conference on Digital Signal Processing, 2011

Low Power FPGA Implementations of JH and Fugue Hash Functions.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

An FPGA Implementation of the ZUC Stream Cipher.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
BLAKE HASH Function Family on FPGA: From the Fastest to the Smallest.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

On the hardware implementation efficiency of SHA-3 candidates.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Low Power FPGA Implementations of 256-bit Luffa Hash Function.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
Editorial: Special Issue on "Information Security and Data Protection in Future Generation Communication and Networking".
Wirel. Pers. Commun., 2009

2008
The Self-synchronizing Stream Cipher Moustique.
Proceedings of the New Stream Cipher Designs - The eSTREAM Finalists, 2008

Secure multimedia communication.
Secur. Commun. Networks, 2008

A Hardware Implementation of CURUPIRA Block Cipher for Wireless Sensors.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
UMTS security: system architecture and hardware implementation.
Wirel. Commun. Mob. Comput., 2007

Guest Editors' Introduction to the Special Issue on Security of Computers and Networks.
Comput. Electr. Eng., 2007

An FPGA-based implementation of the Pomaranch stream cipher.
Proceedings of the 3rd International Conference on Mobile Multimedia Communications, 2007

A System-on-Chip Design of the RadioGatún Hash Function.
Proceedings of the International Conference on High Performance Computing, 2007

A high-speed hardware implementation of the Hermes8-128 stream cipher.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006
Design, Architecture and Performance Evaluation of the Wireless Transport Layer Security.
J. Supercomput., 2006

Architectures and FPGA Implementations of the 64-Bit MISTY1 Block Cipher.
J. Circuits Syst. Comput., 2006

2005
An Fpga Implementation of the Gprs Encryption Algorithm 3 (gea3).
J. Circuits Syst. Comput., 2005

Comparison of the Hardware Implementation of Stream Ciphers.
Int. Arab J. Inf. Technol., 2005

On the Hardware Implementation of the MICKEY-128 Stream Cipher.
IACR Cryptol. ePrint Arch., 2005

Cryptography: Circuits and Systems Approach.
Proceedings of the Integrated Circuit and System Design, 2005

A RAM-based FPGA implementation of the 64-bit MISTY1 block cipher.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Efficient architecture and hardware implementation of the Whirlpool hash function.
IEEE Trans. Consumer Electron., 2004

Open Mobile Alliance (OMA) Security Layer: Architecture, Implementation and Performance Evaluation of the Integrity Unit.
New Gener. Comput., 2004

Configurable Hardware Implementations of Bulk Encryption Units for Wireless Communications.
Int. Arab J. Inf. Technol., 2004

64-bit Block ciphers: hardware implementations and comparison analysis.
Comput. Electr. Eng., 2004

Whirlpool hash function: architecture and VLSI implementation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

High-speed hardware implementations of the KASUMI block cipher.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

High performance cryptographic engine PANAMA: hardware implementation.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Comparison of the hardware architectures and FPGA implementations of stream ciphers.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

2003
Hardware Implementation of Bluetooth Security.
IEEE Pervasive Comput., 2003

An efficient reconfigurable multiplier architecture for Galois field GF(2<sup>m</sup>).
Microelectron. J., 2003

An reconfigurable multiplier in GF(2<sup>m</sup>) for elliptic curve cryptosystem.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

VLSI implementations of the triple-DES block cipher.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

2002
Random number generator architecture and VLSI implementation.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Hardware implementation of the SAFER+ encryption algorithm for the Bluetooth system.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Euclidean algorithm VLSI implementations.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

VLSI implementation of password (PIN) authentication unit.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

An efficient implementation of the digital signature algorithm.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001
A reconfigurable linear feedback shift register (LFSR) for the Bluetooth system.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001


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