Ipoom Jeong

Orcid: 0000-0001-7513-2858

According to our database1, Ipoom Jeong authored at least 25 papers between 2017 and 2025.

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Bibliography

2025
Time Series Machine Learning Models for Precise SSD Access Latency Prediction.
IEEE Comput. Archit. Lett., 2025

Intel ® in-Memory Analytics Accelerator: Performance Characterization and Guidelines.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2025

A4: Microarchitecture-Aware LLC Management for Datacenter Servers with Emerging I/O Devices.
Proceedings of the 52nd Annual International Symposium on Computer Architecture, 2025

UPP: Universal Predicate Pushdown to Smart Storage.
Proceedings of the 52nd Annual International Symposium on Computer Architecture, 2025

Marching Page Walks: Batching and Concurrent Page Table Walks for Enhancing GPU Throughput.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025

Warped-Compaction: Maximizing GPU Register File Bandwidth Utilization via Operand Compaction.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025

2024
Triple-A: Early Operand Collector Allocation for Maximizing GPU Register Bank Utilization.
IEEE Embed. Syst. Lett., June, 2024

Demystifying a CXL Type-2 Device: A Heterogeneous Cooperative Computing Perspective.
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

Intel Accelerators Ecosystem: An SoC-Oriented Perspective : Industry Product.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

HAL: Hardware-assisted Load Balancing for Energy-efficient SNIC-Host Cooperative Computing.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

ScaleCache: A Scalable Page Cache for Multiple Solid-State Drives.
Proceedings of the Nineteenth European Conference on Computer Systems, 2024

TAROT: A CXL SmartNIC-Based Defense Against Multi-bit Errors by Row-Hammer Attacks.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

A Quantitative Analysis and Guidelines of Data Streaming Accelerator in Modern Intel Xeon Scalable Processors.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
A convertible neural processor supporting adaptive quantization for real-time neural networks.
J. Syst. Archit., December, 2023

A Quantitative Analysis and Guideline of Data Streaming Accelerator in Intel 4th Gen Xeon Scalable Processors.
CoRR, 2023

Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices.
CoRR, 2023

LADIO: Leakage-Aware Direct I/O for I/O-Intensive Workloads.
IEEE Comput. Archit. Lett., 2023

Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

INTERPRET: Inter-Warp Register Reuse for GPU Tensor Core.
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023

2022
CASH-RF: A Compiler-Assisted Hierarchical Register File in GPUs.
IEEE Embed. Syst. Lett., 2022

TEA-RC: Thread Context-Aware Register Cache for GPUs.
IEEE Access, 2022

Reconstructing Out-of-Order Issue Queue.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

2020
CASINO Core Microarchitecture: Generating Out-of-Order Schedules Using Cascaded In-Order Scheduling Windows.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

2019
OverCome: Coarse-Grained Instruction Commit with Handover Register Renaming.
IEEE Trans. Computers, 2019

2017
Parallel in-order execution architecture for low-power processor.
Proceedings of the International SoC Design Conference, 2017


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