Joon-Sung Yang

IEEE Access, 2023

Boosting Semi-Supervised Learning by bridging high and low-confidence predictions.

[BibT_eX]

[DOI]

Khanh-Binh Nguyen

Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023

VSCHH 2023: A Benchmark for the View Synthesis Challenge of Human Heads.

[BibT_eX]

[DOI]

Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023

VECOM: Variation-Resilient Encoding and Offset Compensation Schemes for Reliable ReRAM-Based DNN Accelerator.

[BibT_eX]

[DOI]

Je-Woo Jang

Thai-Hoang Nguyen

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

PIE-DRAM: Postponing IECC to Enhance DRAM performance with access table.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

RQ-DNN: Reliable Quantization for Fault-tolerant Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

ADAPT: A Write Disturbance-Aware Programming Technique for Scaled Phase Change Memory.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

CEnT: An Efficient Architecture to Eliminate Intra-Array Write Disturbance in PCM.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

Checkerboard Dropout: A Structured Dropout With Checkerboard Pattern for Convolutional Neural Networks.

[BibT_eX]

[DOI]

Khanh-Binh Nguyen

Jaehyuk Choi

IEEE Access, 2022

DynaPAT: A Dynamic Pattern-Aware Encoding Technique for Robust MLC PCM-Based Deep Neural Networks.

[BibT_eX]

[DOI]

Thai-Hoang Nguyen

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Value-aware Parity Insertion ECC for Fault-tolerant Deep Neural Network.

[BibT_eX]

[DOI]

Seo-Seok Lee

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Bipolar vector classifier for fault-tolerant deep neural networks.

[BibT_eX]

[DOI]

Suyong Lee

Insu Choi

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Reliability Enhanced Heterogeneous Phase Change Memory Architecture for Performance and Energy Efficiency.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2021

Low-Cost and Effective Fault-Tolerance Enhancement Techniques for Emerging Memories-Based Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs.

[BibT_eX]

[DOI]

Inayat Ullah

IEEE Trans. Very Large Scale Integr. Syst., 2020

Virtual-Tile-Based Flip-Flop Alignment Methodology for Clock Network Power Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

Pattern-Aware Encoding for MLC PCM Storage Density, Energy Efficiency, and Performance Enhancement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Cost-Effective Reliable MLC PCM Architecture Using Virtual Data Based Error Correction.

[BibT_eX]

[DOI]

IEEE Access, 2020

Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits.

[BibT_eX]

[DOI]

IEEE Access, 2020

Reliable and Lightweight PUF-based Key Generation using Various Index Voting Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Effective Write Disturbance Mitigation Encoding Scheme for High-density PCM.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Factored Radix-8 Systolic Array for Tensor Processing.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

PAIR: Pin-aligned In-DRAM ECC architecture using expandability of Reed-Solomon code.

[BibT_eX]

[DOI]

Sangmok Jeong

SeungYup Kang

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Weight Partitioning for Dynamic Fixed-Point Neuromorphic Computing Systems.

[BibT_eX]

[DOI]

Yongshin Kang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Simplifying Deep Neural Networks for FPGA-Like Neuromorphic Systems.

[BibT_eX]

[DOI]

Taehwan Shin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Flipcy: Efficient Pattern Redistribution for Enhancing MLC PCM Reliability and Storage Density.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

MRLoc: Mitigating Row-hammering based on memory Locality.

[BibT_eX]

[DOI]

Jung Min You

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

DRIS-3: Deep Neural Network Reliability Improvement Scheme in 3D Die-Stacked Memory based on Fault Analysis.

[BibT_eX]

[DOI]

Jae-San Kim

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Computation Offloading of Acoustic Model for Client-Edge-Based Speech-Recognition.

[BibT_eX]

[DOI]

Young-Min Lee

Proceedings of the 2019 International Conference on Compliers, 2019

2018

Clock Network Optimization With Multibit Flip-Flop Generation Considering Multicorner Multimode Timing Constraint.

[BibT_eX]

[DOI]

David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Mitigating Observability Loss of Toggle-Based X-Masking via Scan Chain Partitioning.

[BibT_eX]

[DOI]

Sae-Eun Kim

IEEE Trans. Computers, 2018

READ: Reliability Enhancement in 3D-Memory Exploiting Asymmetric SER Distribution.

[BibT_eX]

[DOI]

Hyunseung Han

IEEE Trans. Computers, 2018

New library development method by FSM based cell pattern extraction.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2018

Heterogeneous PCM array architecture for reliability, performance and lifetime enhancement.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Bayesian theory based switching probability calculation method of critical timing path for on-chip timing slack monitoring.

[BibT_eX]

[DOI]

Byung-Su Kim

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Optimized I/O determinism for emerging NVM-based NVMe SSD in an enterprise system.

[BibT_eX]

[DOI]

Seonbong Kim

Proceedings of the 55th Annual Design Automation Conference, 2018

Test cost reduction for <i>X</i>-value elimination by scan slice correlation analysis.

[BibT_eX]

[DOI]

Hyunsu Chae

Proceedings of the 55th Annual Design Automation Conference, 2018

System level performance analysis and optimization for the adaptive clocking based multi-core processor.

[BibT_eX]

[DOI]

Byung-Su Kim

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

BIRA With Optimal Repair Rate Using Fault-Free Memory Region for Area Reduction.

[BibT_eX]

[DOI]

Chang-Hyun Oh

Sae-Eun Kim

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Enhancing Test Compression With Dependency Analysis for Multiple Expansion Ratios.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Exploiting Unused Spare Columns and Replaced Columns to Enhance Memory ECC.

[BibT_eX]

[DOI]

Hyunseung Han

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Physical-aware gating element insertion for thermal-safe scan shift operation.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

Non-linear library characterization method for FinFET logic cells by L1-minimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

PUFSec: Device fingerprint-based security architecture for Internet of Things.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Conference on Computer Communications, 2017

MVP ECC : Manufacturing process variation aware unequal protection ECC for memory reliability.

[BibT_eX]

[DOI]

Seung-Yeob Lee

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Improving NVMe SSD I/O determinism with PCIe virtual channel: work-in-progress.

[BibT_eX]

[DOI]

Seonbong Kim

Proceedings of the 2017 International Conference on Compilers, 2017

2016

Enhancing Superset X-Canceling Method With Relaxed Constraints on Fault Observation.

[BibT_eX]

[DOI]

Jinsuk Chung

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Temperature and voltage droop-aware test scheduling during scan shift operation.

[BibT_eX]

[DOI]

YongJoon Kim

IEICE Electron. Express, 2016

Subthreshold 8T SRAM sizing utilizing short-channel V<sub>t</sub> roll-off and inverse narrow-width effect.

[BibT_eX]

[DOI]

Ik Joon Chang

IEICE Electron. Express, 2016

Memory ECC architecutre utilizing memory column spares.

[BibT_eX]

[DOI]

Jong Hyuk Park

Proceedings of the International SoC Design Conference, 2016

eFuse based IC authentication architecture.

[BibT_eX]

[DOI]

Seung-Yeob Lee

Proceedings of the International SoC Design Conference, 2016

Multi-bit flip-flop generation considering multi-corner multi-mode timing constraint.

[BibT_eX]

[DOI]

JongWon Yi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

AFSEM: Advanced frequent subcircuit extraction method by graph mining approach for optimized cell library developments.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Reducing control bit overhead for X-masking/X-canceling hybrid architecture via pattern partitioning.

[BibT_eX]

[DOI]

Jin-Hyun Kang

Proceedings of the 53rd Annual Design Automation Conference, 2016

A BIRA using fault-free memory region for area reduction.

[BibT_eX]

[DOI]

Chang-Hyun Oh

Sae-Eun Kim

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

System-level failure simulation and memory allocation scheme in 3D memory.

[BibT_eX]

[DOI]

Jung-Jin Lee

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015

Devil in a box: Installing backdoors in electronic door locks.

[BibT_eX]

[DOI]

Proceedings of the 13th Annual Conference on Privacy, Security and Trust, 2015

Robust via-programmable ROM design based on 45nm process considering process variation and enhancement Vmin and yield.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Asymmetric ECC organization in 3D-memory via spare column utilization.

[BibT_eX]

[DOI]

Hyunseung Han

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014

Utilizing ATE Vector Repeat With Linear Decompressor for Test Vector Compression.

[BibT_eX]

[DOI]

Jinkyu Lee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

3-D Probe: Low-Cost Variation Modeling Using Intertest-Item Correlations.

[BibT_eX]

[DOI]

Yonghyun Kim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Communication-aware custom topology generation for VFI network-on-chip.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

Low-power shared memory architecture power mode for mobile system-on-chip.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

2013

Improved Trace Buffer Observation via Selective Data Capture Using 2-D Compaction for Post-Silicon Debug.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Robust Buffered Clock Tree Synthesis by Sensitivity Based Link Insertion.

[BibT_eX]

[DOI]

Ik Joon Chang

IEICE Trans. Electron., 2013

Enhanced algorithm of combining trace and scan signals in post-silicon validation.

[BibT_eX]

[DOI]

Kihyuk Han

Jacob A. Abraham

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Dynamic Trace Signal Selection for Post-Silicon Validation.

[BibT_eX]

[DOI]

Kihyuk Han

Jacob A. Abraham

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

2012

X-Canceling MISR Architectures for Output Response Compaction With Unknown Values.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Test Point Insertion with Control Points Driven by Existing Functional Flip-Flops.

[BibT_eX]

[DOI]

Benoit Nadeau-Dostie

IEEE Trans. Computers, 2012

Bit-error rate improvement of TLC NAND Flash using state re-ordering.

[BibT_eX]

[DOI]

Ik Joon Chang

IEICE Electron. Express, 2012

2011

Efficient Function Mapping in Nanoscale Crossbar Architecture.

[BibT_eX]

[DOI]

Rudrajit Datta

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

2009

Automated Selection of Signals to Observe for Efficient Silicon Debug.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

An industrial case study for X-canceling MISR.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE International Test Conference, 2009

Test point insertion using functional flip-flops to drive control points.

[BibT_eX]

[DOI]

Benoit Nadeau-Dostie

Proceedings of the 2009 IEEE International Test Conference, 2009

Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points.

[BibT_eX]

[DOI]

Benoit Nadeau-Dostie

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008

Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Enhancing Silicon Debug via Periodic Monitoring.

[BibT_eX]

[DOI]