Ivo Schanstra

According to our database1, Ivo Schanstra authored at least 10 papers between 1994 and 2004.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2004
Influence of Bit Line Twisting on the Faulty Behavior of DRAMs.
Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

2003
Consequences of RAM Bitline Twisting for Test Coverage.
Proceedings of the 2003 Design, 2003

2002
Address and Data Scrambling: Causes and Impact on Memory Tests.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

1999
Industrial evaluation of stress combinations for march tests applied to SRAMs.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
Semiconductor manufacturing process monitoring using built-in self-test for embedded memories.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1996
Towards a Uniform Notation for Memory Tests.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Functional test for shifting-type FIFOs.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
Fault models and tests for Ring Address Type FIFOs.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

An Effective BIST Scheme for Ring-Address Type FIFOs.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Functional Tests for Ring-Address SRAM-type FIFOs.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994


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