Ad J. van de Goor

According to our database, Ad J. van de Goor authored at least 131 papers between 1969 and 2011.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2011

Generic, orthogonal and low-cost March Element based memory BIST.

Ad J. van de Goor, Said Hamdioui, Halil Kukner

Proceedings of the 2011 IEEE International Test Conference, 2011

2010

MBIST architecture framework based on orthogonal constructs.

Ad J. van de Goor, Said Hamdioui

Proceedings of the 5th International Design and Test Workshop, 2010

Advanced embedded memory testing: Reducing the defect per million level at lower test cost.

Said Hamdioui, Ad J. van de Goor

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Low-cost, customized and flexible SRAM MBIST engine.

Ad J. van de Goor, Christian Jung, Said Hamdioui, Georgi Gaydadjiev

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Using a CISC microcontroller to test embedded memories.

Ad J. van de Goor, Said Hamdioui, Georgi Gaydadjiev

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Memory testing with a RISC microcontroller.

Ad J. van de Goor, Georgi Gaydadjiev, Said Hamdioui

Proceedings of the Design, Automation and Test in Europe, 2010

2009

New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults.

Ad J. van de Goor, Said Hamdioui, Georgi Nedeltchev Gaydadjiev, Zaid Al-Ars

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs.

Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, Georg Mueller

Proceedings of the 2008 IEEE International Test Conference, 2008

2006

Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs.

Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, Sultan M. Al-Harbi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Opens and Delay Faults in CMOS RAM Address Decoders.

Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor

IEEE Trans. Computers, 2006

DRAM-Specific Space of Memory Tests.

Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, Georgi Gaydadjiev, Jörg E. Vollrath

Proceedings of the 2006 IEEE International Test Conference, 2006

Space of DRAM fault models and corresponding testing.

Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Impact of stresses on the fault coverage of memory tests.

Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, Rob Wadsworth

Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

Framework for Fault Analysis and Test Generation in DRAMs.

Zaid Al-Ars, Said Hamdioui, Georg Mueller, Ad J. van de Goor

Proceedings of the 2005 Design, 2005

2004

Linked faults in random access memories: concept, fault models, test algorithms, and industrial results.

Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, Mike Rodgers

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Memory Fault Modeling Trends: A Case Study.

Said Hamdioui, Rob Wadsworth, John Delos Reyes, Ad J. van de Goor

J. Electron. Test., 2004

An Industrial Evaluation of DRAM Tests.

Ad J. van de Goor

IEEE Des. Test Comput., 2004

Effects of Bit Line Coupling on the Faulty Behavior of DRAMs.

Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

The State-of-Art and Future Trends in Testing Embedded Memories.

Said Hamdioui, Georgi Gaydadjiev, Ad J. van de Goor

Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

The Effectiveness of the Scan Test and Its New Variants.

Ad J. van de Goor, Said Hamdioui, Zaid Al-Ars

Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

Influence of Bit Line Twisting on the Faulty Behavior of DRAMs.

Zaid Al-Ars, Martin Herzog, Ivo Schanstra, Ad J. van de Goor

Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

Detecting Faults in the Peripheral Circuits and an Evaluation of SRAM Tests.

Ad J. van de Goor, Said Hamdioui, Rob Wadsworth

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Tests for address decoder delay faults in RAMs due to inter-gate opens.

Ad J. van de Goor, Said Hamdioui, Zaid Al-Ars

Proceedings of the 9th European Test Symposium, 2004

Soft Faults and the Importance of Stresses in Memory Testing.

Zaid Al-Ars, Ad J. van de Goor

Proceedings of the 2004 Design, 2004

2003

Test generation and optimization for DRAM cell defects using electrical simulation.

Zaid Al-Ars, Ad J. van de Goor

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

A Systematic Method for Modifying March Tests for Bit-Oriented Memories into Tests for Word-Oriented Memories.

Ad J. van de Goor, Issam B. S. Tlili

IEEE Trans. Computers, 2003

Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs.

Zaid Al-Ars, Ad J. van de Goor

IEEE Trans. Computers, 2003

Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests.

Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, Mike Rodgers

J. Electron. Test., 2003

Detecting Intra-Word Faults in Word-Oriented Memories.

Said Hamdioui, Ad J. van de Goor, Mike Rodgers

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

A Fault Primitive Based Analysis of Linked Faults in RAMs.

Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor

Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003

Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes.

Zaid Al-Ars, Ad J. van de Goor

Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003

Importance of dynamic faults for new SRAM technologies.

Said Hamdioui, Rob Wadsworth, John Delos Reyes, Ad J. van de Goor

Proceedings of the 8th European Test Workshop, 2003

TPI for improving PR fault coverage of Boolean and three-state circuits.

M. J. Geuzebroek, Ad J. van de Goor

Proceedings of the 8th European Test Workshop, 2003

Consequences of RAM Bitline Twisting for Test Coverage.

Ivo Schanstra, Ad J. van de Goor

Proceedings of the 2003 Design, 2003

Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation.

Zaid Al-Ars, Ad J. van de Goor, Jens Braun, Detlev Richter

Proceedings of the 2003 Design, 2003

March SL: A Test For All Static Linked Memory Faults.

Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, Mike Rodgers

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces.

Zaid Al-Ars, Ad J. van de Goor

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Thorough testing of any multiport memory with linear tests.

Said Hamdioui, Ad J. van de Goor

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Efficient Tests for Realistic Faults in Dual-Port SRAMs.

Said Hamdioui, Ad J. van de Goor

IEEE Trans. Computers, 2002

Testing Static and Dynamic Faults in Random Access Memories.

Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Approximating Infinite Dynamic Behavior for DRAM Cell Defects.

Zaid Al-Ars, Ad J. van de Goor

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

March SS: A Test for All Static Simple RAM Faults.

Said Hamdioui, Ad J. van de Goor, Mike Rodgers

Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume.

M. J. Geuzebroek, J. Th. van der Linden, Ad J. van de Goor

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Address and Data Scrambling: Causes and Impact on Memory Tests.

Ad J. van de Goor, Ivo Schanstra

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Minimal Test for Coupling Faults in Word-Oriented Memories.

Ad J. van de Goor, Magdy S. Abadir, Alan Carlin

Proceedings of the 2002 Design, 2002

Modeling Techniques and Tests for Partial Faults in Memory Devices.

Zaid Al-Ars, Ad J. van de Goor

Proceedings of the 2002 Design, 2002

DRAM Specific Approximation of the Faulty Behavior of Cell Defects.

Zaid Al-Ars, Ad J. van de Goor

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Realistic Fault Models and Test Procedures for Multi-Port SRAMs.

Said Hamdioui, Ad J. van de Goor, David Eastwick, Mike Rodgers

Proceedings of the 9th IEEE International Workshop on Memory Technology, 2001

Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests.

Zaid Al-Ars, Ad J. van de Goor

Proceedings of the 9th IEEE International Workshop on Memory Technology, 2001

Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMs.

Zaid Al-Ars, Ad J. van de Goor, Jens Braun, Detlev Richter

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs.

Zaid Al-Ars, Ad J. van de Goor

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Tests for Resistive and Capacitive Defects in Address Decoders.

Matthias Klaus, Ad J. van de Goor

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Detecting Unique Faults in Multi-port SRAMs.

Said Hamdioui, Ad J. van de Goor, David Eastwick, Mike Rodgers

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Simulation and Development of Short Transparent Tests for RAM.

Serge N. Demidenko, Ad J. van de Goor, S. Henderson, P. Knoppers

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

A Memory Specific Notation for Fault Modeling.

Zaid Al-Ars, Ad J. van de Goor, Jens Braun, Detlev Richter

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy.

Said Hamdioui, Ad J. van de Goor

J. Electron. Test., 2000

Functional Memory Faults: A Formal Notation and a Taxonomy.

Ad J. van de Goor, Zaid Al-Ars

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

March Tests for Realistic Faults in Two-Port Memories.

Said Hamdioui, Ad J. van de Goor, Mike Rodgers, David Eastwick

Proceedings of the 8th IEEE International Workshop on Memory Technology, 2000

Industrial evaluation of DRAM SIMM tests.

Ad J. van de Goor, A. Paalvast

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Test point insertion for compact test sets.

M. J. Geuzebroek, J. Th. van der Linden, Ad J. van de Goor

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

An experimental analysis of spot defects in SRAMs: realistic fault models and tests.

Said Hamdioui, Ad J. van de Goor

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Impact of memory cell array bridges on the faulty behavior in embedded DRAMs.

Zaid Al-Ars, Ad J. van de Goor

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

Designing a Memory Module Tester.

Daniel P. Van der Velde, Ad J. van de Goor

Proceedings of the 7th IEEE International Workshop on Memory Technology, 1999

Testability of the Philips 80C51 micro-controller.

M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Port interference faults in two-port memories.

Said Hamdioui, Ad J. van de Goor

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Industrial evaluation of stress combinations for march tests applied to SRAMs.

Ad J. van de Goor, Ivo Schanstra

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Illegal State Space Identification for Sequential Circuit Test Generation.

M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor

Proceedings of the 1999 Design, 1999

Industrial Evaluation of DRAM Tests.

Ad J. van de Goor, J. de Neef

Proceedings of the 1999 Design, 1999

Fault (In)Dependent Cost Estimates and Conflict-Directed Backtracking to Guide Sequential Circuit Test Generation.

M. H. Konijnenburg, Hans van der Linden, Ad J. van de Goor

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

March Tests for Word-Oriented Two-Port Memories.

Said Hamdioui, Ad J. van de Goor

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

Defining SRAM Resistive Defects and Their Simulation Stimuli.

Ad J. van de Goor, J. E. Simonse

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

Automatic fault localization at chip level.

R. D. L. Stout, Ad J. van de Goor, R. E. Wolff

Microprocess. Microsystems, 1998

Fault Models and Tests for Two-Port Memories.

Ad J. van de Goor, Said Hamdioui

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Semiconductor manufacturing process monitoring using built-in self-test for embedded memories.

Ivo Schanstra, Dharmajaya Lukita, Ad J. van de Goor, Kees Veelenturf, Paul J. van Wijnen

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Consequences of port restrictions on testing two-port memories.

Said Hamdioui, Ad J. van de Goor

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

March Tests for Word-Oriented Memories.

Ad J. van de Goor, Issam B. S. Tlili

Proceedings of the 1998 Design, 1998

Complete Search in Test Generation for Industrial Circuits with Improved Bus-Conflict Detection.

J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

Consequences of Port Restriction on Testing Address Decoders in Two-Port Memories.

Said Hamdioui, Ad J. van de Goor

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

Answers to the Key Issues.

Ad J. van de Goor

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

Disturb Neighborhood Pattern Sensitive Fault.

Ad J. van de Goor, Issam B. S. Tlili

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Sequential Test Generation with Advanced Illegal State Search.

M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

The Implementation of Pseudo-Random Memory Tests on Commercial Memory Testers.

Ad J. van de Goor, Mike Lin

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

March LA: a test for linked memory faults.

Ad J. van de Goor, Georgi Gaydadjiev, Vyacheslav N. Yarmolik, V. G. Mikitjuk

Proceedings of the European Design and Test Conference, 1997

1996

March LR: a test for realistic linked faults.

Ad J. van de Goor, Georgi Gaydadjiev, V. G. Mikitjuk, Vyacheslav N. Yarmolik

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Accelerated Compact Test Set Generation for Three-State Circuits.

M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

RAM Testing Algorithm for Detection Linked Coupling Faults.

V. G. Mikitjuk, V. N. Yarmolik, Ad J. van de Goor

Proceedings of the 1996 European Design and Test Conference, 1996

Towards a Uniform Notation for Memory Tests.

Ad J. van de Goor, Aad Offerman, Ivo Schanstra

Proceedings of the 1996 European Design and Test Conference, 1996

Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Restrictors.

J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

Realistic Linked Memory Cell Array Faults.

Ad J. van de Goor, Georgi Gaydadjiev

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995

Compact test sets for industrial circuits.

M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Coping with Re-usability Using Sequential ATPG: A Practical Case Study.

Jos van Sas, Erik Huyskens, Hans Naert, Fred Schell, Ad J. van de Goor

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Pseudo-exhaustive word-oriented DRAM testing.

Mark G. Karpovsky, Ad J. van de Goor, V. N. Yarmolik

Proceedings of the 1995 European Design and Test Conference, 1995

Functional test for shifting-type FIFOs.

Ad J. van de Goor, Ivo Schanstra, Yervant Zorian

Proceedings of the 1995 European Design and Test Conference, 1995

1994

Fast multiplication in VLSI using wave pipelining techniques.

Fabian Klass, Michael J. Flynn, Ad J. van de Goor

J. VLSI Signal Process., 1994

Effective march algorithms for testing single-order addressed memories.

Ad J. van de Goor, Yervant Zorian

J. Electron. Test., 1994

Test generation and three-state elements, buses, and bidirectionals.

J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Fault models and tests for Ring Address Type FIFOs.

Ad J. van de Goor, Ivo Schanstra, Yervant Zorian

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Automating the verification of memory tests.

Ad J. van de Goor, B. Smit

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

An Effective BIST Scheme for Ring-Address Type FIFOs.

Yervant Zorian, Ad J. van de Goor, Ivo Schanstra

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Parallel Pattern Fast Fault Simulation for Three-State Circuits and Bidirectional I/O.

J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Generating March Tests Automatically.

Ad J. van de Goor, B. Smit

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

A 16x16-bit Static CMOS Wave-Pipelined Multiplier.

Fabian Klass, Michael J. Flynn, Ad J. van de Goor

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Functional Tests for Ring-Address SRAM-type FIFOs.

Ad J. van de Goor, Yervant Zorian, Ivo Schanstra

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993

Using March Tests to Test SRAMs.

Ad J. van de Goor

IEEE Des. Test Comput., 1993

Test Pattern Generation with Restrictors.

M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

1992

Functional Testing of Current Microprocessors (applied to the Intel i860^TM).

Ad J. van de Goor, Th. J. W. Verhallen

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991

A low-cost tester for boundary scan.

Ad J. van de Goor, J. A. M. van Tetering

Microprocess. Microsystems, 1991

Locating Bridging Faults in Memory Arrays.

Ad J. van de Goor, P. C. M. van der Arend, Gert-Jan Tromp

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Truth Table Verification for one-Dimensional CMOS ILA's.

Vlad. Hert, Ad J. van de Goor

Proceedings of the Fault-Tolerant Computing Systems, Tests, Diagnosis, 1991

Logic Synthesis of 100-percent Testable Logic Networks.

Gert-Jan Tromp, Ad J. van de Goor

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1990

The Delft test system.

P. P. Meiler, Ad J. van de Goor

Microprocessing and Microprogramming, 1990

Self test for the Intel 8085.

Ad J. van de Goor, O. Jansen

Microprocessing and Microprogramming, 1990

Special architecture for high-performance scan conversion.

P. B. Franken, Ad J. van de Goor

Microprocessing and Microprogramming, 1990

An Overview of Deterministic Functional RAM Chip Testing.

Ad J. van de Goor, C. A. Verruijt

ACM Comput. Surv., 1990

1989

TLS: a system for building and controlling transputer networks.

M. A. van Peursem, P. Knoppers, Ad J. van de Goor

Microprocessing and Microprogramming, 1989

Distributed system design using Ada as a tool for prototyping.

A. M. Levy, Adrianus J. van de Goor, Jan van Katwijk

Microprocessing and Microprogramming, 1989

DOAS: an object oriented architecture supporting secure languages.

Ad J. van de Goor, Henk Corporaal

Proceedings of the 22nd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1989

Computer architecture and design.

Ad J. van de Goor

Electronic systems engineering series, Addison-Wesley, ISBN: 978-0-201-18241-5, 1989

1988

Test Pattern Generation for API Faults in RAM.

Petra De Jong, Ad J. van de Goor

IEEE Trans. Computers, 1988

Software transparent cache consistency scheme for a VMEbus-based system.

Reinder J. Bril, Ad J. van de Goor

Microprocess. Microsystems, 1988

Transputer network with flexible topology.

P. Knoppers, Ad J. van de Goor, O. M. Gunhildsbu, P. Stravers

Microprocess. Microprogramming, 1988

Speech synthesis system with unlimited vocabulary for the Dutch language.

Ad J. van de Goor, G. J. Nanninga

Microprocess. Microprogramming, 1988

UNIX I/O in a Multiprocessor System.

Ad J. van de Goor, A. Moolenaar

Proceedings of the USENIX Winter Conference. Dallas, Texas, USA, January 1988, 1988

1987

Amore Address Mapping with Overlapped Rotating Entries.

G. J. Dekker, Ad J. van de Goor

IEEE Micro, 1987

Using the page mode of dynamic RAMs to obtain a pseudo cache.

T. A. Peelen, Ad J. van de Goor

Microprocess. Microsystems, 1987

Multiprocessing memory subsystem.

Ad J. van de Goor, A. C. van Wijngaarden

Microprocess. Microsystems, 1987

1986

Comments on Morris's Starvation-Free Solution to the Mutual Exclusion Problem.

J. K. Annot, M. D. Janssens, Ad J. van de Goor

Inf. Process. Lett., 1986

Adapting UNIX for a Multiprocessor Environment.

M. D. Janssens, J. K. Annot, Ad J. van de Goor

Commun. ACM, 1986

1984

Effects of technical developments on system security.

Ad J. van de Goor

Comput. Secur., 1984

1969

Design and Behavior of TSS/8: a PDP-8 Based Time-Sharing System.

Ad J. van de Goor, C. Gordon Bell, Donald A. Witcraft

IEEE Trans. Computers, 1969

A Control Unit for a DEC PDP-8 Computer and a Burroughs Disk.

Ad J. van de Goor, C. Gordon Bell

IEEE Trans. Computers, 1969