Zaid Al-Ars

According to our database1, Zaid Al-Ars authored at least 118 papers between 2000 and 2020.

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Bibliography

2020
Exploring Complex Brain-Simulation Workloads on Multi-GPU Deployments.
TACO, 2020

2019
ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA.
Signal Processing Systems, 2019

Frame-based Programming, Stream-Based Processing for Medical Image Processing Applications.
Signal Processing Systems, 2019

ALMARVI System Solution for Image and Video Processing in Healthcare, Surveillance and Mobile Applications.
Signal Processing Systems, 2019

Evaluation of the Impact of Technology Scaling on Delay Testing for Low-Cost AVS.
J. Electronic Testing, 2019

Correction to: GASAL2: a GPU accelerated sequence alignment library for high-throughput NGS data.
BMC Bioinformatics, 2019

GASAL2: a GPU accelerated sequence alignment library for high-throughput NGS data.
BMC Bioinformatics, 2019

Fletcher: A Framework to Efficiently Integrate FPGA Accelerators with Apache Arrow.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

A Fine-Grained Parallel Snappy Decompressor for FPGAs Using a Relaxed Execution Model.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

The FitOptiVis ECSEL project: highly efficient distributed embedded image/video processing in cyber-physical systems.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

Refine and Recycle: A Method to Increase Decompression Parallelism.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow.
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019

2018
Hardware acceleration of BWA-MEM genomic short read mapping for longer read lengths.
Computational Biology and Chemistry, 2018

Porting and Benchmarking of BWAKIT Pipeline on OpenPOWER Architecture.
Proceedings of the High Performance Computing, 2018

GPU-based stochastic-gradient optimization for non-rigid medical image registration in time-critical applications.
Proceedings of the Medical Imaging 2018: Image Processing, 2018

Cost Effective Adaptive Voltage Scaling Using Path Delay Fault Testing.
Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

An industrial case study of low cost adaptive voltage scaling using delay test patterns.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Industrial evaluation of transition fault testing for cost effective offline adaptive voltage scaling.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

A high-bandwidth snappy decompressor in reconfigurable logic: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018

An Efficient GPU-Based de Bruijn Graph Construction Algorithm for Micro-Assembly.
Proceedings of the 18th IEEE International Conference on Bioinformatics and Bioengineering, 2018

Comparative Analysis of System-Level Acceleration Techniques in Bioinformatics: A Case Study of Accelerating the Smith-Waterman Algorithm for BWA-MEM.
Proceedings of the 18th IEEE International Conference on Bioinformatics and Bioengineering, 2018

Evaluating Auto-adaptation Methods for Fine-Grained Adaptable Processors.
Proceedings of the Architecture of Computing Systems - ARCS 2018, 2018

2017
Pushing Big Data into Accelerators: Can the JVM Saturate Our Hardware?
Proceedings of the High Performance Computing, 2017

Towards real-time whisker tracking in rodents for studying sensorimotor disorders.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Using transition fault test patterns for cost effective offline performance estimation.
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

GPU accelerated API for alignment of genomics sequencing data.
Proceedings of the 2017 IEEE International Conference on Bioinformatics and Biomedicine, 2017

GPU-Accelerated GATK HaplotypeCaller with Load-Balanced Multi-Process Optimization.
Proceedings of the 17th IEEE International Conference on Bioinformatics and Bioengineering, 2017

Streaming Distributed DNA Sequence Alignment Using Apache Spark.
Proceedings of the 17th IEEE International Conference on Bioinformatics and Bioengineering, 2017

High Performance Streaming Smith-Waterman Implementation with Implicit Synchronization on Intel FPGA using OpenCL.
Proceedings of the 17th IEEE International Conference on Bioinformatics and Bioengineering, 2017

Predictive Genome Analysis Using Partial DNA Sequencing Data.
Proceedings of the 17th IEEE International Conference on Bioinformatics and Bioengineering, 2017

SparkGA: A Spark Framework for Cost Effective, Fast and Accurate DNA Analysis at Scale.
Proceedings of the 8th ACM International Conference on Bioinformatics, 2017

VLIW-Based FPGA Computation Fabric with Streaming Memory Hierarchy for Medical Imaging Applications.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

2016
An Efficient GPUAccelerated Implementation of Genomic Short Read Mapping with BWAMEM.
SIGARCH Computer Architecture News, 2016

BrainFrame: A node-level heterogeneous accelerator platform for neuron simulations.
CoRR, 2016

Power-efficiency analysis of accelerated BWA-MEM implementations on heterogeneous computing platforms.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Industrial approaches for performance evaluation using on-chip monitors.
Proceedings of the 11th International Design & Test Symposium, 2016

Power-Efficient Accelerated Genomic Short Read Mapping on Heterogeneous Computing Platforms.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

Challenges of using on-chip performance monitors for process and environmental variation compensation.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Exploration of alternative GPU implementations of the pair-HMMs forward algorithm.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2016

Maximizing systolic array efficiency to accelerate the PairHMM Forward Algorithm.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2016

A comparison of seed-and-extend techniques in modern DNA read alignment algorithms.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2016

Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector.
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

GPU-Accelerated BWA-MEM Genomic Mapping Algorithm Using Adaptive Load Balancing.
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

2015
Scalability Potential of BWA DNA Mapping Algorithm on Apache Spark.
Proceedings of the 2nd Annual International Symposium on Information Management and Big Data, 2015

An FPGA-based systolic array to accelerate the BWA-MEM genomic mapping algorithm.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Using VLIW softcore processors for image processing applications.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Calculation of worst-case execution time for multicore processors using deterministic execution.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

Heterogeneous Hardware/Software Acceleration of the BWA-MEM DNA Alignment Algorithm.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Accelerating complex brain-model simulations on GPU platforms.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

FPGA acceleration of the pair-HMMs forward algorithm for DNA sequence analysis.
Proceedings of the 2015 IEEE International Conference on Bioinformatics and Biomedicine, 2015

Cluster-based Apache Spark implementation of the GATK DNA analysis pipeline.
Proceedings of the 2015 IEEE International Conference on Bioinformatics and Biomedicine, 2015

Heterogeneous Hardware Accelerators with Hybrid Interconnect: An Automated Design Approach.
Proceedings of the 2015 International Conference on Advanced Computing and Applications, 2015

2014
Efficent and highly portable deterministic multithreading (DetLock).
Computing, 2014

Automated Hybrid Interconnect Design for FPGA Accelerators Using Data Communication Profiling.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

A Survey on Low-Power Techniques for Single and Multicore Systems.
Proceedings of the 3rd International Conference on Context-Aware Systems and Applications, 2014

2013
Fault tolerance on multicore processors using deterministic multithreading.
Proceedings of the 8th International Design and Test Symposium, 2013

Accurate and efficient identification of worst-case execution time for multicore processors: A survey.
Proceedings of the 8th International Design and Test Symposium, 2013

Reducing random-dopant fluctuation impact on core-speed and power variability in many-core platforms.
Proceedings of the 8th International Design and Test Symposium, 2013

Hybrid interconnect design for heterogeneous hardware accelerators.
Proceedings of the Design, Automation and Test in Europe, 2013

Efficient software-based fault tolerance approach on multicore platforms.
Proceedings of the Design, Automation and Test in Europe, 2013

Heterogeneous hardware accelerators interconnect: An overview.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

2012
DetLock: Portable and Efficient Deterministic Execution for Shared Memory Multicore Systems.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

A heuristic-based communication-aware hardware optimization approach in heterogeneous multicore systems.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Rule-based data communication optimization using quantitative communication profiling.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

A user-level library for fault tolerance on shared memory multicore systems.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
Survey of fault tolerance techniques for shared memory multicore/multiprocessor systems.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

4-D parity codes for soft error correction in aerospace applications.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs.
Proceedings of the 16th European Test Symposium, 2011

GPU-accelerated protein sequence alignment.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

Influence of parasitic memory effect on single-cell faults in SRAMs.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Testing for Parasitic Memory Effect in SRAMs.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

A New Test Paradigm for Semiconductor Memories in the Nano-Era.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Bit line coupling memory tests for single-cell fails in SRAMs.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

INDEXYS, a Logical Step beyond GENESYS.
Proceedings of the Computer Safety, 2010

Detecting memory faults in the presence of bit line coupling in SRAM devices.
Proceedings of the 2011 IEEE International Test Conference, 2010

Parasitic memory effect in CMOS SRAMs.
Proceedings of the 5th International Design and Test Workshop, 2010

Performance and bandwidth optimization for biological sequence alignment.
Proceedings of the 5th International Design and Test Workshop, 2010

2009
New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

Fault Diagnosis Using Test Primitives in Random Access Memories.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
Test Set Development for Cache Memory in Modern Microprocessors.
IEEE Trans. VLSI Syst., 2008

Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs.
Proceedings of the 2008 IEEE International Test Conference, 2008

Automating defects simulation and fault modeling for SRAMs.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

Acceleration of Smith-Waterman using Recursive Variable Expansion.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
Optimizing Test Length for Soft Faults in DRAM Devices.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

PPM Reduction on Embedded Memories in System on Chip.
Proceedings of the 12th European Test Symposium, 2007

Manifestation of Precharge Faults in High Speed DRAM Devices.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006
Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Opens and Delay Faults in CMOS RAM Address Decoders.
IEEE Trans. Computers, 2006

DRAM-Specific Space of Memory Tests.
Proceedings of the 2006 IEEE International Test Conference, 2006

Space of DRAM fault models and corresponding testing.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Impact of stresses on the fault coverage of memory tests.
Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

Framework for Fault Analysis and Test Generation in DRAMs.
Proceedings of the 2005 Design, 2005

Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
Linked faults in random access memories: concept, fault models, test algorithms, and industrial results.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Effects of Bit Line Coupling on the Faulty Behavior of DRAMs.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

The Effectiveness of the Scan Test and Its New Variants.
Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

Influence of Bit Line Twisting on the Faulty Behavior of DRAMs.
Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

Tests for address decoder delay faults in RAMs due to inter-gate opens.
Proceedings of the 9th European Test Symposium, 2004

Soft Faults and the Importance of Stresses in Memory Testing.
Proceedings of the 2004 Design, 2004

Evaluation of Intra-Word Faults in Word-Oriented RAMs.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
Test generation and optimization for DRAM cell defects using electrical simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs.
IEEE Trans. Computers, 2003

Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests.
J. Electronic Testing, 2003

A Fault Primitive Based Analysis of Linked Faults in RAMs.
Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003

Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes.
Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003

Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation.
Proceedings of the 2003 Design, 2003

March SL: A Test For All Static Linked Memory Faults.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
Testing Static and Dynamic Faults in Random Access Memories.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Approximating Infinite Dynamic Behavior for DRAM Cell Defects.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Modeling Techniques and Tests for Partial Faults in Memory Devices.
Proceedings of the 2002 Design, 2002

DRAM Specific Approximation of the Faulty Behavior of Cell Defects.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests.
Proceedings of the 9th IEEE International Workshop on Memory Technology, 2001

Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMs.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

A Memory Specific Notation for Fault Modeling.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
Functional Memory Faults: A Formal Notation and a Taxonomy.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Impact of memory cell array bridges on the faulty behavior in embedded DRAMs.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000


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