Yervant Zorian

According to our database1, Yervant Zorian authored at least 226 papers between 1984 and 2018.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 1999, "For contributions to built-in self-test of complex devices and systems.".

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
Guest Editor's Introduction.
IEEE Design & Test, 2018

IP session on ISO26262 EDA.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

2017
Guest Editors' Introduction: Design & Test of a High-Volume 3-D Stacked Graphics Processor With High-Bandwidth Memory.
IEEE Design & Test, 2017

Keynotes: Robustness challenges in the internet of things.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

An effective functional safety solution for automotive systems-on-chip.
Proceedings of the IEEE International Test Conference, 2017

Advanced functional safety mechanisms for embedded memories and IPs in automotive SoCs.
Proceedings of the IEEE International Test Conference, 2017

Advanced ECC solution for automotive SoCs.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

An effective functional safety infrastructure for system-on-chips.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Experimental study on Hamming and Hsiao codes in the context of embedded applications.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

Automated flow for test pattern creation for IPs in SoC.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

An efficient testing methodology for embedded flash memories.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

2016
Welcome to the IDT 2016.
Proceedings of the 11th International Design & Test Symposium, 2016

Securing test infrastructure of system-on-chips.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016


2015
Impact of parameter variations on FinFET faults.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Message from the LATS2015 Chairs.
Proceedings of the 16th Latin-American Test Symposium, 2015

An effective embedded test & diagnosis solution for external memories.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

The future of fault tolerant computing.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Keynote 3: "Ensuring robustness in today's IoT era".
Proceedings of the 10th International Design & Test Symposium, 2015

Overview study on fault modeling and test methodology development for FinFET-based memories.
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

An efficient approach for memory repair by reducing the number of spares.
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

A power based memory BIST grouping methodology.
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

2014
Guest Editors' Introduction: Highlights of the 50th DAC.
IEEE Design & Test, 2014

Special session 12C: Young professionals in test - Town meeting.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Fault modeling and test algorithm creation strategy for FinFET-based memories.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Design, test & repair methodology for FinFET-based memories.
Proceedings of the 2014 International Test Conference, 2014

Extending fault periodicity table for testing faults in memories under 20nm.
Proceedings of the 2014 East-West Design & Test Symposium, 2014

2013
Special session 12C: Town-hall meeting "young professionals in test".
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

An effective solution for building memory BIST infrastructure based on fault periodicity.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Integrating embedded test infrastructure in SRAM cores to detect aging.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

An efficient fault diagnosis and localization algorithm for Successive-Approximation Analog to Digital Converters.
Proceedings of the East-West Design & Test Symposium, 2013

Impact of process variations on read failures in SRAMs.
Proceedings of the East-West Design & Test Symposium, 2013

Application of defect injection flow for fault validation in memories.
Proceedings of the East-West Design & Test Symposium, 2013

2012
A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Guest Editorial: Special Issue on Testing of 3D Stacked Integrated Circuits.
J. Electronic Testing, 2012

Message From the Steering Committee.
IEEE Design & Test of Computers, 2012

Design for test and reliability in ultimate CMOS.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Addressing Test Challenges in Advanced Technology Nodes.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
12th "IEEE Latin-American Test Workshop" Porto de Galinhas, Brazil, 27-30 March 2011.
J. Low Power Electronics, 2011

Symmetry Measure for Memory Test and Its Application in BIST Optimization.
J. Electronic Testing, 2011

Generic BIST architecture for testing of content addressable memories.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

A Robust Solution for Embedded Memory Test and Repair.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Test and reliability concerns for 3D-ICs.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

An efficient March test for detection of all two-operation dynamic faults from subclass Sav.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

2009
Guest Editor's Introduction: Examples of Management Decision Criteria.
IEEE Design & Test of Computers, 2009

Guest Editors' Introduction: The Status of IEEE Std 1500 - Part 2.
IEEE Design & Test of Computers, 2009

IEEE Std 1500 Enables Modular SoC Testing.
IEEE Design & Test of Computers, 2009

Guest Editors' Introduction: The Status of IEEE Std 1500.
IEEE Design & Test of Computers, 2009

Testing 3D chips containing through-silicon vias.
Proceedings of the 2009 IEEE International Test Conference, 2009

Panel Session - Vertical integration versus disaggregation.
Proceedings of the Design, Automation and Test in Europe, 2009

DFM: don't care or competitive weapon?
Proceedings of the 46th Design Automation Conference, 2009

2008
IEEE Standard 1500 Compliance Verification for Embedded Cores.
IEEE Trans. VLSI Syst., 2008

An Efficient March-Based Three-Phase Fault Location and Full Diagnosis Algorithm for Realistic Two-Operation Dynamic Faults in Random Access Memories.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

2007
Minimal March Tests for Detection of Dynamic Faults in Random Access Memories.
J. Electronic Testing, 2007

A March-based Fault Location Algorithm with Partial and Full Diagnosis for All Simple Static Faults in Random Access Memories.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Making Manufacturing Work For You.
Proceedings of the 44th Design Automation Conference, 2007

2006
Guest Editors' Introduction: Big Innovations in Small Packages.
IEEE Design & Test of Computers, 2006

Session Abstract.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Session Abstract.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Minimal March Tests for Dynamic Faults in Random Access Memories.
Proceedings of the 11th European Test Symposium, 2006

Minimal March-Based Fault Location Algorithm with Partial Diagnosis for all Static Faults in Random Access Memories.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Decision-making for complex SoCs in consumer electronic products.
Proceedings of the 43rd Design Automation Conference, 2006

Tradeoffs and choices for emerging SoCs in high-end applications.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Guest Editors' Introduction: DFM Drives Changes in Design Flow.
IEEE Design & Test of Computers, 2005

Nanoscale Design & Test Challenges.
IEEE Computer, 2005

SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Minimal March Tests for Unlinked Static Faults in Random Access Memories.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Optimizing SoC Manufacturability.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

IEEE 1500 utilization in SOC design and test.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Today's SOC test challenges.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Impact of Soft Error Challenge on SoC Design.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

On-Line Testing for Secure Implementations: Design and Validation.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Semiconductor Industry Disaggregation vs Reaggregation: Who Will be the Shark?
Proceedings of the 2005 Design, 2005

Challenges in Embedded Memory Design and Test.
Proceedings of the 2005 Design, 2005

Choosing flows and methodologies for SoC design.
Proceedings of the 42nd Design Automation Conference, 2005

How to determine the necessity for emerging solutions.
Proceedings of the 42nd Design Automation Conference, 2005

T1: Design for Manufacturability.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
Fault isolation for nonisolated blocks.
IEEE Trans. VLSI Syst., 2004

Distributed Diagnosis of Interconnections in SoC and MCM Designs.
J. Electronic Testing, 2004

Guest Editors' Introduction: Design for Yield and Reliability.
IEEE Design & Test of Computers, 2004

SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure.
IEEE Design & Test of Computers, 2004

Design & Test Education in Asia.
IEEE Design & Test of Computers, 2004

2003 Technology Roadmap for Semiconductors.
IEEE Computer, 2004

Reducing Embedded SRAM Test Time under Redundancy Constraints.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

A Methodology for Design and Evaluation of Redundancy Allocation Algorithms.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Embedded Memory Reliability: The SER Challenge.
Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

Investment vs. Yield Relationship for Memories in SOC.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
Instruction-Based Self-Testing of Processor Cores.
J. Electronic Testing, 2003

Easily Testable Cellular Carry Lookahead Adders.
J. Electronic Testing, 2003

Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield.
IEEE Design & Test of Computers, 2003

IEEE CASS becomes D&T Copublisher.
IEEE Design & Test of Computers, 2003

Guest Editor's Introduction: Advances in Infrastructure IP.
IEEE Design & Test of Computers, 2003

A Hierarchical Infrastructure for SoC Test Management.
IEEE Design & Test of Computers, 2003

A Test Interface for Built-In Test of Non-Isolated Scanned Cores.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Yield Threats and Inadequacy of One-time Test.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Overview of the IEEE P1500 Standard.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Low-Cost Software-Based Self-Testing of RISC Processor Cores.
Proceedings of the 2003 Design, 2003

Leveraging Infrastructure IP for SoC Yield.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
On IEEE P1500's Standard for Embedded Core Test.
J. Electronic Testing, 2002

2001 Technology Roadmap for Semiconductors.
IEEE Computer, 2002

Instruction-Based Self-Testing of Processor Cores.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

A March-Based Fault Location Algorithm for Static Random Access Memories.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

Embedded Memory Test and Repair: Infrastructure IP for SOC Yield.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

A March-Based Fault Location Algorithm for Static Random Access Memories.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Fault Isolation Using Tests for Non-Isolated Blocks.
Proceedings of the 2002 Design, 2002

Effective Software Self-Test Methodology for Processor Cores.
Proceedings of the 2002 Design, 2002

Embedding infrastructure IP for SOC yield improvement.
Proceedings of the 39th Design Automation Conference, 2002

2001
Switching activity generation with automated BIST synthesis forperformance testing of interconnects.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Boundary Scan-Based Relay Wave Propagation Test of Arrays of Identical Structures.
IEEE Trans. Computers, 2001

A Discussion on Test Pattern Generation for FPGA - Implemented Circuits.
J. Electronic Testing, 2001

An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths.
J. Electronic Testing, 2001

EIC Message.
IEEE Design & Test of Computers, 2001

Error-Free Products.
IEEE Design & Test of Computers, 2001

Huge Storage Capacity.
IEEE Design & Test of Computers, 2001

Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

An Approach for Evaluation of Redunancy Analysis Algorithms.
Proceedings of the 9th IEEE International Workshop on Memory Technology, 2001

IS-FPGA : a new symmetric FPGA architecture with implicit scan.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

System-on-Chip: Embedded Test Strategies.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Embedded tutorial: TRP: integrating embedded test and ATE.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Deterministic software-based self-testing of embedded processor cores.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays.
IEEE Trans. Computers, 2000

Testing the Local Interconnect Resources of SRAM-Based FPGA's.
J. Electronic Testing, 2000

An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family.
J. Electronic Testing, 2000

A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures.
J. Electronic Testing, 2000

Wider Coverage.
IEEE Design & Test of Computers, 2000

Embedded in this issue.
IEEE Design & Test of Computers, 2000

Flexibility and Programmability.
IEEE Design & Test of Computers, 2000

Power-/Energy Efficient BIST Schemes for Processor Data Paths.
IEEE Design & Test of Computers, 2000

Low Power/Energy BIST Scheme for Datapaths.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Wrapper design for embedded core test.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

On using IEEE P1500 SECT for test plug-n-play.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Different experiments in test generation for XILINX FPGAs.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

HD/sup 2/BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Embedded-Quality for Test.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Test of Future System-on-Chips.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000


Yield Improvement and Repair Trade-Off for Large Embedded Memories.
Proceedings of the 2000 Design, 2000

Effective Low Power BIST for Datapaths.
Proceedings of the 2000 Design, 2000

System chip test: how will it impact your design?
Proceedings of the 37th Conference on Design Automation, 2000

TOF: a tool for test pattern generation optimization of an FPGA application oriented test.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

SoC Testing and P1500 Standard.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
An Effective Built-In Self-Test Scheme for Parallel Multipliers.
IEEE Trans. Computers, 1999

SRAM-Based FPGAs: Testing the Embedded RAM Modules.
J. Electronic Testing, 1999

Integration Continues.
IEEE Design & Test of Computers, 1999

D&T Expands.
IEEE Design & Test of Computers, 1999

Focus on DRAMs.
IEEE Design & Test of Computers, 1999

Testing Embedded-Core-Based System Chips.
IEEE Computer, 1999

An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Testing of Non-Isolated Embedded Legacy Cores and their Surrounding Logic.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Towards a standard for embedded core test: an example.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's.
Proceedings of the 1999 Design, 1999

An Effective BIST Architecture for Fast Multiplier Cores.
Proceedings of the 1999 Design, 1999

Scaling Deeper to Submicron: On-Line Testing to the Rescue.
Proceedings of the 1999 Design, 1999

Minimizing the Number of Test Configurations for Different FPGA Families.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998
On-Line Testing for VLSI - A Compendium of Approaches.
J. Electronic Testing, 1998

Efficient Totally Self-Checking Shifter Design.
J. Electronic Testing, 1998

Challenges and Options.
IEEE Design & Test of Computers, 1998

Once Again, a Super Issue.
IEEE Design & Test of Computers, 1998

D&T: 15th Year in Service.
IEEE Design & Test of Computers, 1998

Testing the Interconnect of RAM-Based FPGAs.
IEEE Design & Test of Computers, 1998

Effective Built-In Self-Test for Booth Multipliers.
IEEE Design & Test of Computers, 1998

ITC 97 Panel Sessions.
IEEE Design & Test of Computers, 1998

A D&T Roundtable: Testing Mixed Logic and DRAM Chips.
IEEE Design & Test of Computers, 1998

Robustly Testable Array Multipliers under Realistic Sequential Cell Fault Model.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Testing embedded-core based system chips.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

SRAM-based FPGA's: testing the LUT/RAM modules.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

A distributed BIST technique for diagnosis of MCM interconnections.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Built in self repair for embedded high density SRAM.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Synthesis of BIST hardware for performance testing of MCM interconnections.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

High-level design validation and test.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules.
Proceedings of the Field-Programmable Logic and Applications, 1998

RAM-Based FPGA's: A Test Approach for the Configurable Logic.
Proceedings of the 1998 Design, 1998


Built-In Self-Test with an Alternating Output.
Proceedings of the 1998 Design, 1998

System-Chip Test Strategies (Tutorial).
Proceedings of the 35th Conference on Design Automation, 1998

SRAM-Based FPGA's: Testing the Interconnect/Logic Interface.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
An Effective Multi-Chip BIST Scheme.
J. Electronic Testing, 1997

Fundamentals of MCM Testing and Design-for-Testability.
J. Electronic Testing, 1997

Guest Editorial.
J. Electronic Testing, 1997

Design and Test of Core-Based Systems on Chips.
IEEE Design & Test of Computers, 1997

Introducing Core-Based System Design.
IEEE Design & Test of Computers, 1997

Test of RAM-based FPGA: methodology and application to the interconnect.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Systems On Silicon: Design and Test Challenges.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Power Dissipation During Testing: Should We Worry About it?
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Test Requirements for Embedded Core-Based Systems and IEEE P1500.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

An Effective BIST Scheme for Arithmetic Logic Units.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

On the generation of pseudo-deterministic two-patterns test sequence with LFSRs.
Proceedings of the European Design and Test Conference, 1997

Fault-secure shifter design: results and implementations.
Proceedings of the European Design and Test Conference, 1997

Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996
Programmable BIST Space Compactors.
IEEE Trans. Computers, 1996

Guest Editors' Introduction: East Meets West.
IEEE Design & Test of Computers, 1996

Panel Summaries.
IEEE Design & Test of Computers, 1996

EIC Message.
IEEE Design & Test of Computers, 1996

Conference Reports.
IEEE Design & Test of Computers, 1996

Optimal Multiple Chain Relay Testing Scheme for MCMs on Large Area Substrates.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

An Effective BIST Scheme for Datapaths.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Designing Self-Testable Multi-Chip Modules.
Proceedings of the 1996 European Design and Test Conference, 1996

Relay Propagation Scheme for Testing of MCMs on Large Area Substrates.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Integration of partial scan and built-in self-test.
J. Electronic Testing, 1995

Conference Reports.
IEEE Design & Test of Computers, 1995

An Approach for Designing Total-Dose Tolerant MCMs Based on Current Monitoring.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

An Effective BIST Scheme for Booth Multipliers.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Area versus detection latency trade-offs in self-checking memory design.
Proceedings of the 1995 European Design and Test Conference, 1995

Functional test for shifting-type FIFOs.
Proceedings of the 1995 European Design and Test Conference, 1995

An effective BIST scheme for carry-save and carry-propagate array multipliers.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994
Effective march algorithms for testing single-order addressed memories.
J. Electronic Testing, 1994

Fault models and tests for Ring Address Type FIFOs.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

An Effective BIST Scheme for Ring-Address Type FIFOs.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Do You Practice Safe Tests? What We Found Out About Your Habits.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Functional Tests for Ring-Address SRAM-type FIFOs.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
A distributed BIST control scheme for complex VLSI devices.
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

A Method for Delay Fault Self-Testing of Macrocells.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

PSBIST: A Partial-Scan Based Built-In Self-Test Scheme.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Programmable Space Compaction for BIST.
Proceedings of the Digest of Papers: FTCS-23, 1993

1992
Count-based BIST compaction schemes and aliasing probability computation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

An Effective BIST Scheme for ROM's.
IEEE Trans. Computers, 1992

A Universal Testability Strategy for Multi-Chip Modules Based on BIST and Boundary-Scan.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1990
Optimizing error masking in BIST by output data modification.
J. Electronic Testing, 1990

EEODM: An effective BIST scheme for ROMs.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Computing the Error Escape Probability in Count-Based Compaction Schemes.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1984
Higher Certainty of Error Coverage by Output Data Modification.
Proceedings of the Proceedings International Test Conference 1984, 1984


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