J. Jacob Wikner

Orcid: 0000-0002-2144-6795

According to our database1, J. Jacob Wikner authored at least 47 papers between 2000 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Comparative Analysis of CMOS Latch-Driver Circuits for Current-Steering Digital-to-Analog Converters.
Proceedings of the 29th International Conference on Mixed Design of Integrated Circuits and System, 2022

A Reconfigurable 13.56MHz Wireless Powered CMOS Integrated Nerve Stimulator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
A digital switching scheme to reduce DAC glitches using code-dependent randomization.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2021, Oslo, 2021

2020
A 10-bit 3.75-GS/s Binary-Weighted DAC with 58.6-pJ Energy Consumption in 65-nm CMOS.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2020, Oslo, 2020

2019
Direct digital-to-RF converter employing semi-digital FIR voltage-mode RF DAC.
Integr., 2019

ASIC modelling of SENSE for parallel MRI.
Comput. Biol. Medicine, 2019

NFC Powered Implantable Temperature Sensor.
Proceedings of the 41st Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2019

2017
A high-resolution reconfigurable sigma-delta Digital-to-Analog Converter for RF pulse transmission in MRI scanners.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

Self-oscillating multilevel switched-capacitor DC/DC converter for energy harvesting.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

2016
A 0.4-V Subnanowatt 8-Bit 1-kS/s SAR ADC in 65-nm CMOS for Wireless Sensor Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A low-power wide tuning-range CMOS current-controlled oscillator.
Integr., 2016

Aiming for the cloud - a study of implanted battery-free temperature sensors using NFC.
Proceedings of the International Symposium on Integrated Circuits, 2016

2015
A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer.
Integr., 2015

Digital estimation and compensation method for nonlinearity mismatches in time-interleaved analog-to-digital converters.
Digit. Signal Process., 2015

An ultra-low-voltage OTA in 28 nm UTBB FDSOI CMOS using forward body bias.
Proceedings of the Nordic Circuits and Systems Conference, 2015

Design of a reference voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A wide range all-digital delay locked loop for video applications.
Proceedings of the European Conference on Circuit Theory and Design, 2015

Design of efficient CMOS rectifiers for integrated piezo-MEMS energy-harvesting power management systems.
Proceedings of the European Conference on Circuit Theory and Design, 2015

Realistic path loss estimation for capacitive body-coupled communication.
Proceedings of the European Conference on Circuit Theory and Design, 2015

Complex path impedance estimation and matching requirements for body-coupled communication.
Proceedings of the European Conference on Circuit Theory and Design, 2015

A fully-differential OTA in 28 nm UTBB FDSOI CMOS for PGA applications.
Proceedings of the European Conference on Circuit Theory and Design, 2015

Transfer characteristics and bandwidth limitation in a linear-drift memristor model.
Proceedings of the European Conference on Circuit Theory and Design, 2015

2014
1.2-V Analog Interface for a 300-MSps HD Video Digitizer in Core 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A 1.1-V Analog Multiplexer With an Adaptive Digital Clamp for CMOS Video Digitizers.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Reducing Complexity and Power of Digital Multibit Error-Feedback ΔΣ Modulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Design considerations for interface circuits to low-voltage piezoelectric energy harvesters.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

Design of a sampling switch for a 0.4-V SAR ADC using a multi-stage charge pump.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

Linear programming design of semi-digital FIR filter and ΣΔ modulator for VDSL2 transmitter.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Modeling and analysis of aliasing image spurs problem in digital-RF-converter-based IQ modulators.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A digital-RF converter architecture for IQ modulator with discrete-time low resolution quadrature LO.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012
An analog receiver front-end for capacitive body-coupled communication.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

Study and simulation of an example redundant FIR filter.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

Power efficient arrangement of oversampling sigma-delta DAC.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

2011
Inter-channel offset and gain mismatch correction for time-interleaved pipelined ADCs.
Microelectron. J., 2011

A nonlinearity error calibration technique for pipelined ADCs.
Integr., 2011

Clockless asynchronous delta modulator based ADC for smart dust applications.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

A study on switched-capacitor blocks for reconfigurable ADCs.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

An event-driven 8-bit ADC with a segmented resistor-string DAC.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

A study on power consumption of modified noise-shaper architectures for ΣΔ DACs.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
Calibration of high-resolution flash ADCS based on histogram test methods.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

A 1.2-V pseudo-differential OTA with common-mode feedforward in 65-NM CMOS.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2002
A differential DAC architecture with variable common-mode level.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Design of encoders for linear-coded D/A converters.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Spectral shaping of DAC nonlinearity errors through modulation of expected errors.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Dynamic element matching in D/A converters with restricted scrambling.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

Glitch minimization and dynamic element matching in D/A converters.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000


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