Yasir Ali Shah

Orcid: 0000-0002-5156-5840

According to our database1, Yasir Ali Shah authored at least 10 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2023
Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA Accelerators.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

2022
VLCC-Q: Very low computational complexity optical interconnect architecture with queueing for reducing delay and back pressure probability in data center networks.
Concurr. Comput. Pract. Exp., 2022

2020
LUT-based high-speed point multiplier for Goldilocks-Curve448.
IET Comput. Digit. Tech., 2020

2019
Redundant-Signed-Digit-Based High Speed Elliptic Curve Cryptographic Processor.
J. Circuits Syst. Comput., 2019

Design and Optimization of Complementary Field Excited Linear Flux Switching Machine With Unequal Primary Tooth Width and Segmented Secondary.
IEEE Access, 2019

2018
High-speed FPGA implementation of full-word Montgomery multiplier for ECC applications.
Microprocess. Microsystems, 2018

A high-speed RSD-based flexible ECC processor for arbitrary curves over general prime field.
Int. J. Circuit Theory Appl., 2018

CAMONET: Moth-Flame Optimization (MFO) Based Clustering Algorithm for VANETs.
IEEE Access, 2018

2017
<i>K</i>-means based multiple objects tracking with long-term occlusion handling.
IET Comput. Vis., 2017

2015
A wide range all-digital delay locked loop for video applications.
Proceedings of the European Conference on Circuit Theory and Design, 2015


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