J. K. Wang

According to our database, J. K. Wang authored at least 4 papers between 2011 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes.

Balaji Narasimham, K. Chandrasekharan, J. K. Wang, Bharat L. Bhuva

Proceedings of the IEEE International Reliability Physics Symposium, 2019

2018

Scaling trends and bias dependence of the soft error rate of 16 nm and 7 nm FinFET SRAMs.

Balaji Narasimham, Saket Gupta, Daniel S. Reed, J. K. Wang, Nick Hendrickson, Hasan Taufique

Proceedings of the IEEE International Reliability Physics Symposium, 2018

2017

Analysis of Time Delay Attacks against Power Grid Stability.

J. K. Wang, Chunyi Peng

Proceedings of the 2nd Workshop on Cyber-Physical Security and Resilience in Smart Grids, 2017

2011

Space-alternating generalised expectation-maximisation-based h-infinity channel estimator for multiple-input multiple-output-orthogonal frequency division multiplexing systems.

P. Xu, J. K. Wang, F. Qi, X. Song

IET Commun., 2011