K. Chandrasekharan

According to our database, K. Chandrasekharan authored at least 2 papers between 2008 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2019

Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes.

Balaji Narasimham, K. Chandrasekharan, J. K. Wang, Bharat L. Bhuva

Proceedings of the IEEE International Reliability Physics Symposium, 2019

2008

A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS.

Gregory Uhlmann, Tony Aipperspach, Toshiaki Kirihata, K. Chandrasekharan, Yan Zun Li, Chris Paone, Brian Reed, Norman Robson, John Safran, David Schmitt, Subramanian S. Iyer

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008