Saket Gupta

According to our database, Saket Gupta authored at least 13 papers between 2010 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A Comprehensive Review on STATCOM: Paradigm of Modeling, Control, Stability, Optimal Location, Integration, Application, and Installation.

Sandeep Sharma, Saket Gupta, Mohd Zuhaib, Vijay Bhuria, Hasmat Malik, Abdulaziz Almutairi, Asyraf Afthanorhan, Mohammad Asef Hossaini

IEEE Access, 2024

2018

Scaling trends and bias dependence of the soft error rate of 16 nm and 7 nm FinFET SRAMs.

Balaji Narasimham, Saket Gupta, Daniel S. Reed, J. K. Wang, Nick Hendrickson, Hasan Taufique

Proceedings of the IEEE International Reliability Physics Symposium, 2018

2016

Bitcell-Based Design of On-Chip Process Variability Monitors for Sub-28 nm Memories.

Saket Gupta, Carl Monzel, Daniel S. Reed, Yifei Zhang, Mark Winter, Myron Buer

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

2015

Influence of supply voltage on the multi-cell upset soft error sensitivity of dual- and triple-well 28 nm CMOS SRAMs.

Balaji Narasimham, Jung K. Wang, Narayana Vedula, Saket Gupta, Brandon Bartz, Carl Monzel, Indranil Chatterjee, Bharat L. Bhuva, Ronald D. Schrimpf, Robert A. Reed

Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014

Variation-Aware Variable Latency Design.

Saket Gupta, Sachin S. Sapatnekar

IEEE Trans. Very Large Scale Integr. Syst., 2014

2013

Employing circadian rhythms to enhance power and reliability.

Saket Gupta, Sachin S. Sapatnekar

ACM Trans. Design Autom. Electr. Syst., 2013

BioinQA: metadata-based multi-document QA system for addressing the issues in biomedical domain.

Sparsh Mittal, Saket Gupta, Ankush Mittal

Int. J. Data Min. Model. Manag., 2013

2012

Compact Current Source Models for Timing Analysis Under Temperature and Body Bias Variations.

Saket Gupta, Sachin S. Sapatnekar

IEEE Trans. Very Large Scale Integr. Syst., 2012

Circuit reliability: From Physics to Architectures: Embedded tutorial paper.

Jianxin Fang, Saket Gupta, Sanjay V. Kumar, Sravan K. Marella, Vivek Mishra, Pingqiang Zhou, Sachin S. Sapatnekar

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors.

Ayan Paul, Matt Amrein, Saket Gupta, Arvind Vinod, Abhishek Arun, Sachin S. Sapatnekar, Chris H. Kim

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

BTI-aware design using variable latency units.

Saket Gupta, Sachin S. Sapatnekar

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

GNOMO: Greater-than-NOMinal Vdd operation for BTI mitigation.

Saket Gupta, Sachin S. Sapatnekar

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2010

Current source modeling in the presence of body bias.

Saket Gupta, Sachin S. Sapatnekar

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010